XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 4

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Virtex-II Features
This section briefly describes Virtex-II features.
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
•
•
•
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
•
•
•
•
•
•
•
The digitally controlled impedance (DCI) I/O feature
automatically provides on-chip termination for each I/O
element.
The IOB elements also support the following differential
signaling I/O standards:
•
•
•
•
•
Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:
•
•
•
•
•
•
•
DS122 (v2.0) December 21, 2007
Product Specification
Input block with an optional single-data-rate or double-
data-rate (DDR) register
Output block with an optional single-data-rate or DDR
register, and an optional 3-state buffer, to be driven
directly or through a single or DDR register
Bidirectional block (any combination of input and output
configurations)
LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
PCI compatible (33 MHz) at 3.3V
CardBus compliant (33 MHz) at 3.3V
GTL and GTLP
HSTL (Class I, II, III, and IV)
SSTL (3.3V and 2.5V, Class I and II)
AGP-2X
LVDS
BLVDS (Bus LVDS)
ULVDS
LDT
LVPECL
Two function generators (F and G)
Two storage elements
Arithmetic logic gates
Large multiplexers
Wide function capability
Fast carry look-ahead chain
Horizontal cascade chain (OR gate)
R
www.xilinx.com
The function generators F and G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM memory.In addition, the two storage
elements are either edge-triggered D-type flip-flops or level-
sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Block SelectRAM Memory
The block SelectRAM memory resources are 18 Kb of
dual-port RAM, programmable from 16K x 1 bit to
512 x 36 bits, in various depth and width configurations.
Each port is totally synchronous and independent, offering
three "read-during-write" modes. Block SelectRAM memory
is cascadable to implement large embedded storage blocks.
Supported memory configurations for dual-port and single-
port modes are shown in
Table 3: Dual-Port And Single-Port Configurations
A multiplier block is associated with each SelectRAM
memory block. The multiplier block is a dedicated 18 x 18-
bit multiplier and is optimized for operations based on the
block SelectRAM content on one port. The 18 x 18
multiplier can be used independently of the block
SelectRAM resource. Read/multiply/accumulate operations
and DSP filter structures are extremely efficient.
Both the SelectRAM memory and the multiplier resource
are connected to four switch matrices to access the general
routing resources.
Global Clocking
The DCM and global clock multiplexer buffers provide a
complete solution for designing high-speed clocking schemes.
Up to 12 DCM blocks are available. To generate de-skewed
internal or external clocks, each DCM can be used to
eliminate clock distribution delay. The DCM also provides
90-, 180-, and 270-degree phase-shifted versions of its
output clocks. Fine-grained phase shifting offers high-
resolution phase adjustments in increments of 1/256 of the
clock period. Very flexible frequency synthesis provides a
clock output frequency equal to any M/D ratio of the input
clock frequency, where M and D are two integers. For the
exact timing parameters, see
Characteristics," page
Virtex-II devices have 16 global clock MUX buffers with up
to eight clock nets per quadrant. Each global clock MUX
buffer can select one of the two clock inputs and switch
glitch-free from one clock to the other. Each DCM block is
able to drive up to four of the 16 global clock MUX buffers.
16K x 1 bit
8K x 2 bits
4K x 4 bits
QPro Virtex-II 1.5V Platform FPGAs
53.
Table
"QPro Virtex-II Switching
3.
512 x 36 bits
1K x 18 bits
2K x 9 bits
4