XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 11

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XQ2V1000-4BG575N

Manufacturer Part Number
XQ2V1000-4BG575N
Description
FPGA 650MHZ CMOS1.5V 575-P
Manufacturer
Xilinx Inc
Series
QPro™ Virtex™-IIr
Datasheet

Specifications of XQ2V1000-4BG575N

Number Of Labs/clbs
1280
Total Ram Bits
737280
Number Of I /o
328
Number Of Gates
100000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-55°C ~ 125°C
Package / Case
575-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Other names
Q5801737

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Input/Output Individual Options
Each device pad has optional pull-up and pull-down
resistors in all SelectI/O-Ultra configurations. Each device
pad has an optional weak-keeper in LVTTL, LVCMOS, and
PCI SelectI/O-Ultra configurations, as illustrated in
X-Ref Target - Figure 6
The optional weak-keeper circuit is connected to each output.
When selected, this circuit monitors the voltage on the pad
and weakly drives the pin High or Low. If the pin is connected
to a multiple-source signal, the weak-keeper holds the signal
in its last state if all drivers are disabled. Maintaining a valid
logic level in this way eliminates bus chatter. Pull-up or pull-
down resistors override the weak-keeper circuit.
Table 9: LVTTL and LVCMOS Programmable Currents (Sink and Source)
DS122 (v2.0) December 21, 2007
Product Specification
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
SelectI/O-Ultra
R
Program
Delay
2 mA
2 mA
2 mA
2 mA
2 mA
OBUF
Figure 6: LVTTL, LVCMOS, or PCI SelectI/O-Ultra Standards
Program Current
V CCO
IBUF
4 mA
4 mA
4 mA
4 mA
4 mA
V CCO
Programmable Current (Worst-Case Guaranteed Minimum)
Figure
Clamp
Diode
6 mA
6 mA
6 mA
6 mA
6 mA
www.xilinx.com
6.
10-60KΩ
10-60KΩ
Values of the optional pull-up and pull-down resistors are in
the range 10 - 60 KΩ, which is the specification for V
when operating at 3.3V (from 3.0V to 3.6V only). The clamp
diode is always present, even when power is not.
LVTTL sinks and sources current up to 24 mA. The current
is programmable for LVTTL and LVCMOS SelectI/O-Ultra
standards (see
controls for each output driver minimize bus transients. For
LVDCI and LVDCI_DV2 standards, drive strength and slew-
rate controls are not available.
8 mA
8 mA
8 mA
8 mA
8 mA
V CCO
Table
12 mA
12 mA
12 mA
12 mA
12 mA
Keeper
Weak
QPro Virtex-II 1.5V Platform FPGAs
9). Drive-strength and slew-rate
16 mA
16 mA
16 mA
16 mA
16 mA
V CCAUX = 3.3V
V CCINT = 1.5V
DS031_23_011601
PAD
24 mA
24 mA
24 mA
n/a
n/a
CCO
11

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