XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 36

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

X-Ref Target - Figure 42
BUFGCE
If the CE input is active (High) prior to the incoming rising
clock edge, this Low-to-High-to-Low clock pulse passes
through the clock buffer. Any level change of CE during the
incoming clock High time has no effect.
X-Ref Target - Figure 43
If the CE input is inactive (Low) prior to the incoming rising
clock edge, the following clock pulse does not pass through the
clock buffer, and the output stays Low. Any level change of CE
during the incoming clock High time has no effect. CE must not
change during a short setup window just prior to the rising
clock edge on the BUFGCE input I. Violating this setup time
requirement can result in an undefined runt pulse output.
BUFGMUX
BUFGMUX can switch between two unrelated, even
asynchronous clocks. Basically, a Low on S selects the I0
input, and a High on S selects the I1 input. Switching from
one clock to the other is done in such a way that the output
High and Low time is never shorter than the shortest High or
Low time of either input clock. As long as the presently
selected clock is High, any level change of S has no effect.
If the presently selected clock is Low while S changes, or if
it goes Low after S has changed, the output is kept Low until
the other ("to-be-selected") clock has made a transition
from High to Low. At that instant, the new clock starts
driving the output.
DS122 (v2.0) December 21, 2007
Product Specification
Figure 43: Virtex-II BUFGCE Function
R
CE
I
BUFGCE
NW
SW
DS031_62_101200
8 BUFGMUX
O
16 Clocks
8 BUFGMUX
Figure 42: Virtex-II Clock Distribution
SE
NE
www.xilinx.com
NW
SW
8
8
X-Ref Target - Figure 44
The two clock inputs can be asynchronous with regard to
each other, and the S input can change at any time, except
for a short setup time prior to the rising edge of the presently
selected clock, that is, prior to the rising edge of the
BUFGMUX output O. Violating this setup time requirement
can result in an undefined runt pulse output.
All Virtex-II devices have 16 global clock multiplexer buffers.
Figure 45
Figure
•
•
•
•
•
•
The current clock is CLK0.
S is activated High.
If CLK0 is currently High, the multiplexer waits for CLK0
to go Low.
Once CLK0 is Low, the multiplexer output stays Low
until CLK1 transitions High to Low.
When CLK1 transitions from High to Low, the output
switches to CLK1.
No glitches or short pulses can appear on the output.
8 BUFGMUX
8 BUFGMUX
45:
16 Clocks
Figure 44: Virtex-II BUFGMUX Function
shows a switchover from CLK0 to CLK1. In
S
8
8
I0
I1
QPro Virtex-II 1.5V Platform FPGAs
BUFGMUX
DS031_45_120200
DS031_63_112900
O
8 max
SE
NE
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