XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 42

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Hierarchical Routing Resources
Most Virtex-II signals are routed using the global routing
resources, which are located in horizontal and vertical
routing channels between each switch matrix. As shown in
Figure
programmable interconnections, with a number of
resources counted between any two adjacent switch matrix
rows or columns. Fanout has minimal impact on the
performance of each net.
In
•
X-Ref Target - Figure 50
Dedicated Routing
In addition to the global and local routing resources,
dedicated signals are available:
•
•
DS122 (v2.0) December 21, 2007
Product Specification
Figure
Long lines are bidirectional wires that distribute signals
across the device. Vertical and horizontal long lines
span the full height and width of the device.
There are eight global clock nets per quadrant (see
"Global Clock Multiplexer
Horizontal routing resources are provided for on-chip 3-
state buses. Four partitionable bus lines are provided
per CLB row, permitting multiple buses within a row.
(See
50, Virtex-II devices have fully buffered
"3-State
50:
R
24 Horizontal Long Lines
24 Vertical Long Lines
120 Horizontal Hex Lines
120 Vertical Hex Lines
40 Horizontal Double Lines
40 Vertical Double Lines
16 Direct Connections
(total in all four directions)
8 Fast Connects
Buffers".)
Buffers").
Figure 50: Hierarchical Routing Resources
www.xilinx.com
•
•
•
Fast connect lines are the internal CLB local
interconnections from LUT outputs to LUT inputs.
•
•
•
Hex lines route signals to every third or sixth block away in
all four directions. Organized in a staggered pattern, hex
lines can only be driven from one end. Hex-line signals
can be accessed either at the endpoints or at the midpoint
(three blocks from the source).
Double lines route signals to every first or second block
away in all four directions. Organized in a staggered
pattern, double lines can be driven only at their
endpoints. Double-line signals can be accessed either
at the endpoints or at the midpoint (one block from the
source).
Direct connect lines route signals to neighboring
blocks: vertically, horizontally, and diagonally.
Two dedicated carry-chain resources per slice column
(two per CLB column) propagate carry-chain MUXCY
output signals vertically to the adjacent slice. (See
"CLB/Slice
One dedicated SOP chain per slice row (two per CLB
row) propagates ORCY output logic signals horizontally
to the adjacent slice. (See
One dedicated shift chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See
"Shift
Configurations".)
Registers".)
QPro Virtex-II 1.5V Platform FPGAs
"Sum of
DS031_60_110200
Products".)
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