XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 21

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

X-Ref Target - Figure 18
Distributed SelectRAM Memory
Each function generator (LUT) can implement a 16 x 1-bit
synchronous RAM resource called a distributed SelectRAM
element. The SelectRAM elements are configurable within
a CLB to implement the following:
•
•
•
•
•
•
•
Distributed SelectRAM memory modules are synchronous
(write) resources. The combinatorial read access time is
extremely fast, while the synchronous write simplifies high-
speed designs. A synchronous read can be implemented
with a storage element in the same slice. The distributed
SelectRAM memory and the storage element share the
same clock input. A Write Enable (WE) input is active High,
and is driven by the SR input.
Table 13
occupied by each distributed SelectRAM configuration.
DS122 (v2.0) December 21, 2007
Product Specification
CLK
Figure 18: Register/Latch Configuration in a Slice
CE
SR
Single-port 16 x 8 bit RAM
Single-port 32 x 4 bit RAM
Single-port 64 x 2 bit RAM
Single-port 128 x 1 bit RAM
Dual-port 16 x 4 bit RAM
Dual-port 32 x 2 bit RAM
Dual-port 64 x 1 bit RAM
BY
BX
shows the number of LUTs (two per slice)
R
DX
DY
D
CE
CK
D
CE
CK
SR REV
SR REV
FFY
FFX
FF
LATCH
FF
LATCH
Q
Q
Attribute
Attribute
Reset Type
DS031_22_110600
INIT1
INIT0
SRHIGH
SRLOW
INIT1
INIT0
SRHIGH
SRLOW
SYNC
ASYNC
YQ
XQ
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Table 13: Distributed SelectRAM Configurations
For single-port configurations, distributed SelectRAM
memory has one address port for synchronous writes and
asynchronous reads.
For dual-port configurations, distributed SelectRAM
memory has one port for synchronous writes and
asynchronous reads and another port for asynchronous
reads. The function generator (LUT) has separated read
address inputs (A1, A2, A3, A4) and write address inputs
(WG1/WF1, WG2/WF2, WG3/WF3, WG4/WF4).
In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function
generator (R/W port) is connected with shared read and
write addresses. The second function generator has the A
inputs (read) connected to the second read-only port
address and the W inputs (write) shared with the first
read/write port address.
Figure
illustrate various example configurations.
X-Ref Target - Figure 19
Notes:
1.
S = single-port configuration, and D = dual-port configuration.
WCLK
Figure 19: Distributed SelectRAM (RAM16x1S)
A[3:0]
WE
19,
D
Figure 20, page
128 x 1S
16 x 1S
16 x 1D
32 x 1S
32 x 1D
64 x 1S
64 x 1D
4
(BY)
(SR)
RAM
4
RAM 16x1S
WE
CK
A[4:1]
WG[4:1]
WSG
WS
RAM
QPro Virtex-II 1.5V Platform FPGAs
DI
D
22, and
(optional)
Figure 21, page 22
D
Number of LUTs
Q
1
2
2
4
4
8
8
DS031_02_100900
Output
Registered
Output
21