XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 44

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Design Implementation
The ISE Series development systems include Xilinx timing-
driven implementation tools, frequently called “place and
route” or “fitting” software. This robust suite of tools enables the
creation of an intuitive, flexible, tightly integrated design flow
that efficiently bridges “logical” and “physical” design domains.
This simplifies the task of defining a design, including its
behavior, timing requirements, and optional layout (or
floorplanning), as well as simplifying the task of analyzing
reports generated during the implementation process.
The Virtex-II implementation process is comprised of
Synthesis, translation, mapping, place and route, and
configuration file generation. While the tools can be run
individually, many designers choose to run the entire
implementation process with the click of a button. To assist
those who prefer to script their design flows, Xilinx provides
Xflow, an automated single command line process.
Design Verification
In addition to conventional design verification using static
timing analysis or simulation techniques, Xilinx offers
powerful in-circuit debugging techniques using ChipScope
ILA (Integrated Logic Analysis). The reconfigurable nature
of Xilinx FPGAs means that designs can be verified in real
time without the need for extensive sets of software
simulation vectors.
For simulation, the system extracts post-layout timing
information from the design database, and back-annotates
this information into the netlist for use by the simulator. The
back annotation features a variety of patented Xilinx
techniques, resulting in the industry’s most powerful
simulation flows. Alternatively, timing-critical portions of a
design can be verified using the Xilinx static timing analyzer
or a third party static timing analysis tool like Synopsys
Prime Time, by exporting timing data in the STAMP data
format.
For in-circuit debugging, ChipScope ILA enables designers
to analyze the real-time behavior of a device while operating
at full system speeds. Logic analysis commands and
captured data are transferred between the ChipScope
software and ILA cores within the Virtex-II FPGA, using
industry standard JTAG protocols. These JTAG transactions
are driven over an optional download cable (MultiLINX or
JTAG), connecting the Virtex device in the target system to
a PC or workstation.
ChipScope ILA was designed to look and feel like a logic
analyzer, making it easy to begin debugging a design
immediately. Modifications to the desired logic analysis can be
downloaded directly into the system in a matter of minutes.
DS122 (v2.0) December 21, 2007
Product Specification
R
www.xilinx.com
Other Unique Features of Virtex-II Design
Flow
Xilinx design flows feature a number of unique capabilities.
Among these are efficient incremental HDL design flows,
which are robust capabilities enabled by Xilinx exclusive
hierarchical floorplanning capabilities. Another powerful
design capability only available in the Xilinx design flow is
“Modular Design”, part of the Xilinx suite of team design
tools, which enables autonomous design, implementation,
and verification of design modules.
Incremental Synthesis
Xilinx unique hierarchical floorplanning capabilities enable
designers to create a programmable logic design by
isolating design changes within one hierarchical “logic
block”, and perform synthesis, verification, and
implementation processes on that specific logic block. By
preserving the logic in unchanged portions of a design,
Xilinx incremental design makes the high-density design
process more efficient.
Xilinx hierarchical floorplanning capabilities can be
specified using the high-level floorplanner or a preferred
RTL floorplanner (see the Xilinx website for a list of
supported EDA partners). When used in conjunction with
one of the EDA partners’ floorplanners, higher performance
results can be achieved, as many synthesis tools use this
more predictable detailed physical implementation
information to establish more aggressive and accurate
timing estimates when performing their logic optimizations.
Modular Design
Xilinx innovative modular design capabilities take the
incremental design process one step further by enabling the
designer to delegate responsibility for completing the
design, synthesis, verification, and implementation of a
hierarchical “logic block” to an arbitrary number of designers
- assigning a specific region within the target FPGA for
exclusive use by each of the team members.
This team design capability enables an autonomous
approach to design modules, changing the hand-off point to
the lead designer or integrator from “my module works in
simulation” to “my module works in the FPGA”. This unique
design methodology also leverages the Xilinx hierarchical
floorplanning capabilities and enables the Xilinx (or EDA
partner) floorplanner to manage the efficient
implementation of very high-density FPGAs.
QPro Virtex-II 1.5V Platform FPGAs
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