XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet

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R DS122 (v2.0) December 21, 2007 Summary of QPro™ Virtex™-II Features • Industry’s first military-grade platform FPGA solution • Certified to MIL-PRF-38535 (Qualified Manufacturer Listing) • 100% factory tested • Guaranteed over the full military temperature range (–55°C to +125°C) ...

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... I/Os for each device and package using wire-bond or flip-chip technology. Table 2: Maximum Number of User I/O Pads Device XQ2V1000 XQ2V3000 XQ2V6000 (Table 5, www.xilinx.com QPro Virtex-II 1.5V Platform FPGAs ) core power supply, dedicated 3.3V I/O power supplies ...

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R Architecture Virtex-II Array Overview Virtex-II devices are user-programmable gate arrays with various configurable elements. The Virtex-II architecture is optimized for high-density and high-performance logic designs. As shown in Figure 1, the programmable device is comprised of input/output blocks (IOBs) ...

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R Virtex-II Features This section briefly describes Virtex-II features. Input/Output Blocks (IOBs) IOBs are programmable and can be categorized as follows: • Input block with an optional single-data-rate or double- data-rate (DDR) register • Output block with an optional single-data-rate ...

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R Routing Resources The IOB, CLB, block SelectRAM, multiplier, and DCM elements all use the same interconnect scheme and the same access to the global routing matrix. Timing models are shared, greatly improving the predictability of the performance of high-speed ...

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... DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, DXP, and RSVD) and VBATT. BG575 BG728 & CG717 1.27 1. Available I/Os XQ2V1000 XQ2V3000 324 328 – – – – – www.xilinx.com QPro Virtex-II 1.5V Platform FPGAs ...

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... Epoxy-Coated Flip-Chip BGA Package CF1144 1144-Column Ceramic Flip-Chip Package EF1152 1152-Ball Epoxy-Coated Flip-Chip BGA Package Valid Ordering Combinations M Grade XQ2V3000-4CG717M XQ2V1000-4FG456N (1) XQ2V6000-4CF1144M XQ2V1000-4BG575N XQ2V3000-4BG728N Notes: 1. CF1144 is non-Hermetic Ceramic. DS122 (v2.0) December 21, 2007 Product Specification XQ2V3000 -4 CG 717 M (1) Package N Grade ...

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R Detailed Description Input/Output Blocks (IOBs) Virtex-II I/O blocks (IOBs) are provided in groups of two or four on the perimeter of each device. Each IOB can be used as an input and/or an output for single-ended I/Os. Two IOBs ...

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R Table 8: Supported DCI I/O Standards I/O Output Input Standard V V CCO CCO (1) LVDCI_33 3.3 3.3 (1) LVDCI_DV2_33 3.3 3.3 (1) LVDCI_25 2.5 2.5 (1) LVDCI_DV2_25 2.5 2.5 (1) LVDCI_18 1.8 1.8 (1) LVDCI_DV2_18 1.8 1.8 (1) ...

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R X-Ref Target - Figure CLOCK CLK1 D2 Q2 CLK2 (50/50 duty cycle clock) X-Ref Target - Figure 5 (O/T) 1 (O/T) CE (O/T) CLK1 SR Shared by all registers REV (O/T) CLK2 (O/T) 2 Figure 5: ...

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R Input/Output Individual Options Each device pad has optional pull-up and pull-down resistors in all SelectI/O-Ultra configurations. Each device pad has an optional weak-keeper in LVTTL, LVCMOS, and PCI SelectI/O-Ultra configurations, as illustrated in X-Ref Target - Figure 6 OBUF ...

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R Figure 7 shows the SSTL2, SSTL3, and HSTL configurations. HSTL can sink current mA. (HSTL IV) X-Ref Target - Figure 7 V CCO Clamp OBUF Diode V REF Figure 7: SSTL or HSTL SelectI/O-Ultra Standards All ...

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R X-Ref Target - Figure 9 Bank 1 Bank 0 Bank 4 Bank 5 Figure 9: Virtex-II I/O Banks: Top View for Flip-Chip Packages (FF & BF) V pins within a bank are interconnected internally, and REF consequently only one ...

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R Table 10 summarizes all standards and voltage supplies. Table 10: Summary of Voltage Supply Requirements for All Input and Output Standards V CCO I/O Standard Outpu Inpu t t LVDS_33 LVDSEXT_33 LVPECL_33 N/R SSTL3_I SSTL3_II AGP LVTTL LVCMOS33 LVDCI_33 ...

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R Digitally Controlled Impedance (DCI) Today’s chip output signals with fast edge rates require termination to prevent reflections and maintain signal integrity. High pin count packages (especially ball grid arrays) can not accommodate external termination resistors. Virtex-II XCITE DCI provides ...

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R Figure 12 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O standards. For a complete list, see the X-Ref Target - Figure 12 HSTL_I V CCO /2 R Conventional CCO /2 DCI ...

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R Figure 13 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/O standards. For a complete list, see X-Ref Target - Figure 13 SSTL2_I V /2 CCO R Conventional CCO DCI ...

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R Figure 14 provides examples illustrating the use of the LVDS_DCI and LVDSEXT_DCI I/O standards. For a complete list, see [Ref 1]. X-Ref Target - Figure 14 Conventional Conventional Transmit DCI Receive Reference Resistor Recommended Z 0 DS122 (v2.0) December ...

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R Configurable Logic Blocks (CLBs) The Virtex-II configurable logic blocks (CLB) are organized in an array and are used to build combinatorial and synchronous logic designs. Each CLB element is tied to a switch matrix to access the general routing ...

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R The set and reset functionality of a register or a latch can be configured as follows: • No set or reset • Synchronous set • Synchronous reset • Synchronous set and reset X-Ref Target - Figure 17 SHIFTIN SOPIN ...

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R X-Ref Target - Figure REV CLK SR REV SR BX Figure 18: Register/Latch Configuration in a Slice Distributed SelectRAM Memory Each function generator (LUT) can implement a ...

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R X-Ref Target - Figure 20 RAM 32x1S (BX) A[4] RAM 4 D A[3:0] G[4:1] WG[4: (BY) D WSG WE0 (SR WCLK CK F5MUX WSF WS DI RAM D 4 F[4:1] WF[4:1] Figure 20: Single-Port Distributed ...

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R X-Ref Target - Figure 23 1 Shift Chain in CLB DI IN SRLC16 SRLC16 SLICE S3 DI SRLC16 SRLC16 SLICE S2 SHIFTIN SRLC16 MC15 SRLC16 MC15 SLICE S1 SHIFTOUT SHIFTIN ...

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R X-Ref Target - Figure DS122 (v2.0) December 21, 2007 Product Specification G Slice Slice S2 F Slice S1 Slice S0 CLB Figure 24: MUXF5 and MUXFX multiplexers www.xilinx.com QPro Virtex-II 1.5V ...

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R X-Ref Target - Figure 25 COUT the next CLB (First Carry Chain LUT O I LUT CIN COUT O I LUT O I LUT CIN DS122 (v2.0) December 21, 2007 Product Specification LUT LUT ...

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R Sum of Products Each Virtex-II slice has a dedicated OR gate named ORCY, ORing together outputs from the slices carryout and the ORCY from an adjacent slice. The ORCY gate with the dedicated Sum of Products (SOP) chain are ...

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... SelectRAM memory and multiplier or I/O blocks are skipped. Number of 3-State Buffers Table 15 each Virtex-II device. The number of 3-state buffers is twice Slice the number of CLB elements. S3 Table 15: Virtex-II 3-State Buffers Slice S2 Device XQ2V1000 XQ2V3000 XQ2V6000 DS031_37_060700 Programmable Switch connection matrix CLB-II www.xilinx.com QPro Virtex-II 1.5V Platform FPGAs Figure 29 ...

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... Table 16: Logic Resources in One CLB Slices LUTs Flip-Flops Table 17: Virtex-II Logic Resources Available in All CLBs CLB Array: Number Device Row x of Slices Column XQ2V1000 5,120 XQ2V3000 14,336 XQ2V6000 33,792 Notes: 1. The carry chains and SOP chains can be split or cascaded. DS122 (v2.0) December 21, 2007 Product Specification Table 17 shows the available resources in all CLBs ...

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R 18 Kbit Block SelectRAM Resources Introduction Virtex-II devices incorporate large amounts of 18 Kbit block SelectRAM. These complement the distributed SelectRAM resources that provide shallow RAM structures implemented in CLBs. Each Virtex-II block SelectRAM Kbit true ...

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R Table 19: Dual-Port Mode Configurations Port A 16K x 1 Port B 16K x 1 Port Port Port Port Port ...

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R X-Ref Target - Figure 32 Data_in Data_in Address RAM Contents Data_out X-Ref Target - Figure 33 Data_in Data_in Address RAM Contents Data_out X-Ref Target - Figure 34 Data_in Data_in Address RAM Contents Data_out DS122 (v2.0) December 21, 2007 Product ...

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... Total Amount of SelectRAM Memory Table 23 available for each Virtex-II device. The 18 Kbit SelectRAM blocks are cascadable to implement deeper or wider single- or dual-port memory resources. Table 23: Virtex-II SelectRAM Memory Available Device XQ2V1000 XQ2V3000 XQ2V6000 SelectRAM Blocks SelectRAM Blocks www.xilinx.com QPro Virtex-II 1.5V Platform FPGAs Table 22 ...

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... Kbit block SelectRAM resource. In addition to the built-in multiplier blocks, the CLB elements DS031_33_101000 have dedicated logic to implement efficient multipliers in logic (refer to Table 24: Multiplier Floor Plan Device XQ2V1000 XQ2V3000 XQ2V6000 www.xilinx.com QPro Virtex-II 1.5V Platform FPGAs Figure 37 shows a multiplier block. Multiplier Block ...

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R X-Ref Target - Figure 38 Multiplier Blocks Figure 38: Multipliers (2-column, 4-column, and 6-column) DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs Multiplier Blocks Multiplier Blocks www.xilinx.com DS031_39_101000 34 ...

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R Global Clock Multiplexer Buffers Virtex-II devices have 16 clock input pins that can also be used as regular user I/Os. Eight clock pads are on the top edge of the device, in the middle of the array, and eight ...

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R X-Ref Target - Figure BUFGCE If the CE input is active (High) prior to the incoming rising clock edge, this Low-to-High-to-Low clock pulse passes through the clock buffer. Any level change of CE during the incoming ...

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R X-Ref Target - Figure 45 Wait for Low S CLK0 Switch CLK1 OUT Figure 45: Clock Multiplexer Waveform Diagram DS122 (v2.0) December 21, 2007 Product Specification Local Clocking In addition to global clocks, there are local clock resources in ...

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R Digital Clock Manager (DCM) The Virtex-II DCM offers a wide range of powerful clock management features: • Clock De-skew: The DCM generates new system clocks (either internally or externally to the FPGA), which are phase-aligned to the input clock, ...

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R Phase Shifting The DCM provides additional control over clock skew through either coarse- or fine-grained phase shifting. The CLK0, CLK90, CLK180, and CLK270 outputs are each phase shifted by ¼ of the input clock period relative to each other, ...

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... Table 27. (For actual values, see "QPro Virtex-II Switching Low-Frequency Mode CLK Output CLKOUT_FREQ_1X_LF CLKOUT_FREQ_1X_LF CLKOUT_FREQ_2X_LF CLKOUT_FREQ_DV_LF CLKOUT_FREQ_FX_LF Table 28: DCM Organization Device XQ2V1000 Table 28. XQ2V3000 XQ2V6000 www.xilinx.com QPro Virtex-II 1.5V Platform FPGAs Characteristics".) The High-Frequency Mode CLKIN Input CLK Output CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF ...

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R Active Interconnect Technology Local and global Virtex-II routing resources are optimized for speed and timing predictability, as well as to facilitate IP cores implementation. Virtex-II Active Interconnect Technology is a fully buffered programmable routing matrix. All routing resources are ...

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R Hierarchical Routing Resources Most Virtex-II signals are routed using the global routing resources, which are located in horizontal and vertical routing channels between each switch matrix. As shown in Figure 50, Virtex-II devices have fully buffered programmable interconnections, with ...

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R Creating a Design Creating Virtex-II designs is easy with Xilinx Integrated Synthesis Environment (ISE) development systems, which support advanced design capabilities, including ProActive Timing Closure, integrated logic analysis, and the fastest place and route runtimes in the industry. ISE ...

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... By preserving the logic in unchanged portions of a design, Xilinx incremental design makes the high-density design process more efficient. Xilinx hierarchical floorplanning capabilities can be specified using the high-level floorplanner or a preferred RTL floorplanner (see the Xilinx website for a list of supported EDA partners) ...

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R Configuration Virtex-II devices are configured by loading application- specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be re-used as general ...

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... Daisy chaining is possible only in modes where Serial D daisy chaining of downstream devices. Table 30 lists the total number of bits required to configure each device. Table 30: Virtex-II Bitstream Lengths Device Number of Configuration Bits XQ2V1000 3,753,432 XQ2V3000 9,595,304 XQ2V6000 19,760,560 Notes: 1. These values are only valid for STEPPING LEVEL 1. ...

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R Readback In this mode, configuration data from the Virtex-II FPGA device can be read back. Readback is supported only in the SelectMAP (master and slave) and Boundary Scan modes. Along with the configuration data possible to read ...

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R QPro Virtex-II Electrical Characteristics QPro Virtex-II devices are only available with the -5 and-4 speed grades. QPro Virtex-II DC and AC characteristics are specified for military grade. Except for the operating temperature range, or unless otherwise noted, all the ...

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... XQ2V6000 2 6.25 XQ2V1000 5 40 XQ2V3000 – 10 105 XQ2V6000 12.5 150 [Ref does not power up CCAUX Device (mA) XQ2V1000 XQ2V3000 500 1300 140 140 75 140 values listed here apply to the entire device (all banks). Units V V μA μA pF μA μA nA Units mA ...

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R General Power Supply Requirements Proper decoupling of all FPGA power supplies is essential. Consult [Ref 2] for detailed information on power distribution system design. V powers critical resources in the FPGA. Thus, CCAUX V is especially susceptible to power ...

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R LDT Differential Signal DC Specifications (LDT_25) DC Parameter Differential Output Voltage Change in V Magnitude OD Output Common Mode Voltage Change in V Magnitude OS Input Differential Voltage Change in V Magnitude ID Input Common Mode Voltage Change in ...

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R LVPECL DC Specifications These values are valid when driving a 100 Ω differential load only, i.e., a 100 Ω resistor between the two receiver pins. The V levels are 200 mV below standard LVPECL levels and are compatible with ...

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... QPro Virtex-II device with a corresponding speed grade designation. Table 38: QPro Virtex-II Device Speed Grade Designations Speed Grade Designations Device Advance XQ2V1000 XQ2V3000 XQ2V6000 All specifications are always representative of worst-case supply voltage and junction temperature conditions. Testing of Switching Characteristics All devices are 100% functionally tested ...

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... XQ2V1000 IOPID XQ2V3000 XQ2V6000 T All IOPLI T XQ2V1000 IOPLID XQ2V3000 XQ2V6000 T All IOCKIQ T /T All 0.92/–0.39 IOPICK IOICKP T /T XQ2V1000 3.57/–2.24 IOPICKD IOICKPD XQ2V3000 3.67/–2.31 XQ2V6000 3.97/–2. All 0.21/ 0.04 IOICECK IOCKICE T All IOSRCKI T All IOSRIQ T All GSRQ Table 43 ...

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R IOB Input Switching Characteristics Standard Adjustments Table 40: IOB Input Switching Characteristics Standard Adjustments Description Data Input Delay Adjustments Standard-specific data input delay adjustments DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs Symbol Standard T ...

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R Table 40: IOB Input Switching Characteristics Standard Adjustments (Cont’d) Description Standard-specific data input delay adjustments Notes: 1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II ...

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R IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in Table 41: IOB Output Switching Characteristics ...

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R IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Table 42: IOB Output Switching ...

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R Table 42: IOB Output Switching Characteristics Standard Adjustments (Cont’d) Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs Symbol Standard T ...

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R Table 42: IOB Output Switching Characteristics Standard Adjustments (Cont’d) Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs Symbol Standard T ...

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R Table 43: Delay Measurement Methodology Standard LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 PCI66_3 PCIX33_3 GTL GTLP HSTL Class I HSTL Class II HSTL Class III HSTL Class IV SSTL3 I & II SSTL2 I & II AGP V LVDS_25 ...

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R Table 44: Standard Capacitive Loads LVTTL Fast Slew Rate drive LVTTL Fast Slew Rate drive LVTTL Fast Slew Rate drive LVTTL Fast Slew Rate drive LVTTL Fast Slew Rate ...

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R Clock Distribution Switching Characteristics Table 45: Clock Distribution Switching Characteristics Description Global Clock Buffer I input to O output Global Clock Buffer S input Setup/Hold inputs CLB Switching Characteristics Delays originating at F/G inputs vary ...

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R CLB Distributed RAM Switching Characteristics Table 47: CLB Distributed RAM Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs (WE active mode Clock CLK to X/Y outputs (WE active mode ...

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R Multiplier Switching Characteristics Table 49 and Table 50 provide timing information for QPro Virtex-II multiplier blocks, available in stepping revisions of QPro Virtex-II devices. For more information on stepping revisions, availability, and ordering instructions, see your local sales representative. ...

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R Table 50: Pipelined Multiplier Switching Characteristics Description Setup and Hold Times Before/After Clock Data Inputs Clock Enable Reset Clock to Output Pin Clock to Pin 35 Clock to Pin 34 Clock to Pin 33 Clock to Pin 32 Clock ...

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R Block SelectRAM Switching Characteristics Table 51: Block SelectRAM Switching Characteristics Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times Before Clock CLK ADDR inputs DIN inputs EN input RST input WEN input Clock CLK Minimum Pulse ...

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... For other I/O standards and different loads, see CC www.xilinx.com QPro Virtex-II 1.5V Platform FPGAs Speed Grade Device -5 -4 XQ2V1000 1.28 1.48 XQ2V3000 1.28 1.48 XQ2V6000 1.88 2.17 threshold is with LVCMOS. For other I/O CC Speed Grade Device -5 -4 XQ2V1000 4.28 4.62 XQ2V3000 4.43 5.10 XQ2V6000 5.38 5.93 Units Units ...

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... DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs Symbol Device T /T XQ2V1000 PSDCM PHDCM XQ2V3000 XQ2V6000 Symbol Device T /T XQ2V1000 PSFD PHFD XQ2V3000 XQ2V6000 www.xilinx.com Speed Grade Units -5 -4 1.60/–0.90 1.84/–0.76 ns 1.70/–0.90 1.96/–0.76 ns 1.70/–0.90 1.96/– ...

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R DCM Timing Parameters All devices are 100% functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. ...

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R Input Clock Tolerances Table 59: Input Clock Tolerances Description Input Clock Low/High Pulse Width PSCLK PSCLK_PULSE (2) PSCLK and CLKIN Input Clock Cycle-Cycle Jitter (Low Frequency Mode) (1) CLKIN (using DLL outputs) (2) CLKIN (using CLKFX outputs) Input Clock ...

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R Output Clock Jitter Table 60: Output Clock Jitter Description Clock Synthesis Period Jitter CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180 Notes: 1. Values for this parameter are available at http://www.xilinx.com. Output Clock ...

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R Miscellaneous Timing Parameters Table 62: Miscellaneous Timing Parameters Description Time Required to Achieve LOCK (1) Using DLL outputs Using CLKFX outputs Additional lock time with fine-phase shifting Fine-Phase Shifting Absolute shifting range Delay Lines Tap delay resolution Notes: 1. ...

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... DS122 (v2.0) December 21, 2007 Product Specification Symbol Device T DCD_CLK0 T DCD_CLK180 T XQ2V1000 CKSKEW XQ2V3000 XQ2V6000 Symbol Device/Package T XQ2V6000/CF1144 PKGSKEW Symbol Device T XQ2V1000 SAMP XQ2V3000 XQ2V6000 DCD_CLK180 www.xilinx.com QPro Virtex-II 1.5V Platform FPGAs Speed Grade -5 -4 All 140 140 All 100 110 500 ...

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... These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball. DS122 (v2.0) December 21, 2007 Product Specification Symbol Device T /T XQ2V1000 PSDCM PHDCM XQ2V3000 XQ2V6000 "Source-Synchronous Switching Characteristics" ) QPro Virtex-II Receiver Data-Valid Window (R X ...

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... The number of I/Os per package include all user I/Os except the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, DXP, AND RSVD). Figure 56 for a BG728 & CG717 CF1144 1.27 1. Available I/Os XQ2V1000 XQ2V3000 324 328 – 516 – 516 – – 684 – 720 www ...

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R QPro Virtex-II Pin Definitions This section describes the pinouts for QPro Virtex-II devices in the following packages: • FG456: wire-bond fine-pitch BGA of 1.00 mm pitch • BG575 and BG728: wire-bond BGA of 1.27 mm pitch • CG717: wire-bond ...

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R Table 71: QPro Virtex-II Pin Definitions (Cont’d) Pin Name Direction (1) Dedicated Pins CCLK Input/Output PROG_B Input DONE Input/Output M2, M1, M0 Input HSWAP_EN Input TCK Input TDI Input TDO Output TMS Input PWRDWN_B Input (unsupported) Other Pins DXN, ...

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... R FG456 Fine-Pitch BGA Package The XQ2V1000 QPro Virtex-II device is available in the FG456 fine-pitch BGA package. Pins definitions listed in are identical to the commercial grade XC2V1000-FG456. Following this table are the Specifications (1.00 mm pitch)," page Table 72: FG456 BGA — XQ2V1000 Bank Pin Description ...

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... IO_L46N_2 2 IO_L46P_2 2 IO_L48N_2 2 IO_L48P_2 2 IO_L49N_2 2 IO_L49P_2 2 IO_L51N_2 2 IO_L51P_2/VREF_2 2 IO_L52N_2 2 IO_L52P_2 2 IO_L54N_2 2 IO_L54P_2 DS122 (v2.0) December 21, 2007 Product Specification Table 72: FG456 BGA — XQ2V1000 (Cont’d) Pin Number Bank B18 2 C18 2 D18 2 A19 2 B19 2 2 C21 2 C22 2 E18 F18 3 D21 3 D22 3 E19 ...

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... IO_L22N_4 4 IO_L22P_4 4 IO_L24N_4 4 IO_L24P_4 4 IO_L49N_4 4 IO_L49P_4 4 IO_L51N_4 4 IO_L51P_4/VREF_4 4 IO_L52N_4 4 IO_L52P_4 4 IO_L54N_4 4 IO_L54P_4 DS122 (v2.0) December 21, 2007 Product Specification Table 72: FG456 BGA — XQ2V1000 (Cont’d) Pin Number Bank U18 4 V22 4 V21 4 V20 4 V19 4 W22 4 W21 4 Y22 4 Y21 4 IO_L95N_4/GCLK3S W20 4 IO_L95P_4/GCLK2P AA20 ...

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... IO_L04N_6 6 IO_L06P_6 6 IO_L06N_6 6 IO_L19P_6 6 IO_L19N_6 6 IO_L21P_6 6 IO_L21N_6/VREF_6 6 IO_L22P_6 6 IO_L22N_6 6 IO_L24P_6 6 IO_L24N_6 6 IO_L43P_6 6 IO_L43N_6 6 IO_L45P_6 6 IO_L45N_6/VREF_6 6 IO_L46P_6 6 IO_L46N_6 6 IO_L48P_6 6 IO_L48N_6 DS122 (v2.0) December 21, 2007 Product Specification Table 72: FG456 BGA — XQ2V1000 (Cont’d) Pin Number Bank AA6 AB5 6 AA5 AB4 6 AA4 AA3 ...

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... IO_L01P_7 7 IO_L01N_7 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 DS122 (v2.0) December 21, 2007 Product Specification Table 72: FG456 BGA — XQ2V1000 (Cont’d) Pin Number Bank G11 G10 NA G9 ...

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... VCCINT NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND DS122 (v2.0) December 21, 2007 Product Specification Table 72: FG456 BGA — XQ2V1000 (Cont’d) Pin Number Bank AA1 NA M22 B22 A12 NA U17 T16 NA T15 R16 H16 NA ...

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R FG456 Fine-Pitch BGA Package Specifications (1.00 mm pitch) X-Ref Target - Figure 51 Figure 51: FG456 Fine-Pitch BGA Package Specifications DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs www.xilinx.com 85 ...

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... R BG575 Standard BGA Package The XQ2V1000 QPro Virtex-II device is available in the BG575 BGA package. Following BGA Package Specifications (1.27 mm pitch)," page Table 73: BG575 BGA — XQ2V1000 Bank Pin Description 0 IO_L01N_0 0 IO_L01P_0 0 IO_L02N_0 0 IO_L02P_0 0 IO_L03N_0/VRP_0 0 IO_L03P_0/VRN_0 0 IO_L04N_0/VREF_0 0 IO_L04P_0 0 IO_L05N_0 0 IO_L05P_0 0 IO_L06N_0 ...

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... IO_L04N_2 2 IO_L04P_2 2 IO_L06N_2 2 IO_L06P_2 2 IO_L19N_2 2 IO_L19P_2 2 IO_L21N_2 2 IO_L21P_2/VREF_2 2 IO_L22N_2 2 IO_L22P_2 2 IO_L24N_2 2 IO_L24P_2 2 IO_L43N_2 DS122 (v2.0) December 21, 2007 Product Specification Table 73: BG575 BGA — XQ2V1000 (Cont’d) Pin Number Bank G16 2 A17 2 A19 2 B17 2 B18 2 C17 2 D17 2 F17 2 E17 2 A20 2 A21 2 B19 2 ...

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... IO_L19N_3 3 IO_L19P_3 3 IO_L06N_3 3 IO_L06P_3 3 IO_L04N_3 3 IO_L04P_3 3 IO_L03N_3/VREF_3 3 IO_L03P_3 3 IO_L02N_3/VRP_3 3 IO_L02P_3/VRN_3 3 IO_L01N_3 3 IO_L01P_3 DS122 (v2.0) December 21, 2007 Product Specification Table 73: BG575 BGA — XQ2V1000 (Cont’d) Pin Number Bank R24 R23 4 R22 4 P22 4 P21 4 P20 4 IO_L03N_4/D2/ALT_VRP_4 P18 4 IO_L03P_4/D3/ALT_VRN_4 T24 4 U24 4 T23 4 T22 ...

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... IO_L54N_5 5 IO_L54P_5 5 IO_L52N_5 5 IO_L52P_5 5 IO_L51N_5/VREF_5 5 IO_L51P_5 5 IO_L49N_5 5 IO_L49P_5 5 IO_L24N_5 5 IO_L24P_5 5 IO_L22N_5 5 IO_L22P_5 DS122 (v2.0) December 21, 2007 Product Specification Table 73: BG575 BGA — XQ2V1000 (Cont’d) Pin Number Bank AB13 5 AC13 5 Y13 5 AA13 5 V13 5 W13 5 U14 5 U13 5 5 AD12 5 AD11 5 IO_L03N_5/D4/ALT_VRP_5 AC12 ...

Page 90

... RSVD 6 IO_L91P_6 6 IO_L91N_6 6 IO_L93P_6 6 IO_L93N_6/VREF_6 6 IO_L94P_6 6 IO_L94N_6 6 IO_L96P_6 6 IO_L96N_6 7 IO_L96P_7 7 IO_L96N_7 7 IO_L94P_7 7 IO_L94N_7 7 IO_L93P_7/VREF_7 7 IO_L93N_7 7 IO_L91P_7 7 IO_L91N_7 7 RSVD 7 RSVD 7 RSVD 7 RSVD 7 RSVD 7 RSVD 7 RSVD 7 RSVD DS122 (v2.0) December 21, 2007 Product Specification Table 73: BG575 BGA — XQ2V1000 (Cont’d) Pin Number Bank ...

Page 91

... VCCO_5 6 VCCO_6 6 VCCO_6 6 VCCO_6 6 VCCO_6 6 VCCO_6 6 VCCO_6 7 VCCO_7 7 VCCO_7 7 VCCO_7 7 VCCO_7 7 VCCO_7 7 VCCO_7 DS122 (v2.0) December 21, 2007 Product Specification Table 73: BG575 BGA — XQ2V1000 (Cont’d) Pin Number Bank J15 NA J14 NA J13 NA F14 NA C19 NA B14 NA M16 NA L23 NA L19 NA L16 NA K16 NA F22 NA ...

Page 92

... GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND DS122 (v2.0) December 21, 2007 Product Specification Table 73: BG575 BGA — XQ2V1000 (Cont’d) Pin Number Bank K15 NA K14 NA K13 NA K12 NA K11 NA K10 NA J16 H17 AD24 NA AD23 NA AD18 NA ...

Page 93

R BG575 Standard BGA Package Specifications (1.27 mm pitch) X-Ref Target - Figure 52 Figure 52: BG575 Standard BGA Package Specifications DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs www.xilinx.com 93 ...

Page 94

R BG728 Standard BGA and CG717 Ceramic CGA Packages The XQ2V3000 QPro Virtex-II device is available in the BG728 BGA and CG717 CGA packages. The CG717 has identical pinout as the BG728 (except for those pins listed in ) Table ...

Page 95

R Table 75: BG728 and CG717 — XQ2V3000 (Cont’d) Bank Pin Description 1 IO_L96N_1/GCLK3P 1 IO_L96P_1/GCLK2S 1 IO_L95N_1/GCLK1P 1 IO_L95P_1/GCLK0S 1 IO_L94N_1 1 IO_L94P_1/VREF_1 1 IO_L93N_1 1 IO_L93P_1 1 IO_L92N_1 1 IO_L92P_1 1 IO_L91N_1 1 IO_L91P_1/VREF_1 1 IO_L78N_1 1 IO_L78P_1 ...

Page 96

R Table 75: BG728 and CG717 — XQ2V3000 (Cont’d) Bank Pin Description 2 IO_L27P_2/VREF_2 2 IO_L28N_2 2 IO_L28P_2 2 IO_L30N_2 2 IO_L30P_2 2 IO_L43N_2 2 IO_L43P_2 2 IO_L45N_2 2 IO_L45P_2/VREF_2 2 IO_L46N_2 2 IO_L46P_2 2 IO_L48N_2 2 IO_L48P_2 2 IO_L49N_2 ...

Page 97

R Table 75: BG728 and CG717 — XQ2V3000 (Cont’d) Bank Pin Description 3 IO_L28N_3 3 IO_L28P_3 3 IO_L27N_3/VREF_3 3 IO_L27P_3 3 IO_L25N_3 3 IO_L25P_3 3 IO_L24N_3 3 IO_L24P_3 3 IO_L22N_3 3 IO_L22P_3 3 IO_L21N_3/VREF_3 3 IO_L21P_3 3 IO_L19N_3 3 IO_L19P_3 ...

Page 98

R Table 75: BG728 and CG717 — XQ2V3000 (Cont’d) Bank Pin Description 4 IO_L95P_4/GCLK2P 4 IO_L96N_4/GCLK1S 4 IO_L96P_4/GCLK0P 5 IO_L96N_5/GCLK7S 5 IO_L96P_5/GCLK6P 5 IO_L95N_5/GCLK5S 5 IO_L95P_5/GCLK4P 5 IO_L94N_5 5 IO_L94P_5/VREF_5 5 IO_L93N_5 5 IO_L93P_5 5 IO_L92N_5 5 IO_L92P_5 5 IO_L91N_5 ...

Page 99

R Table 75: BG728 and CG717 — XQ2V3000 (Cont’d) Bank Pin Description 6 IO_L24N_6 6 IO_L25P_6 6 IO_L25N_6 6 IO_L27P_6 6 IO_L27N_6/VREF_6 6 IO_L28P_6 6 IO_L28N_6 6 IO_L43P_6 6 IO_L43N_6 6 IO_L45P_6 6 IO_L45N_6/VREF_6 6 IO_L46P_6 6 IO_L46N_6 6 IO_L48P_6 ...

Page 100

R Table 75: BG728 and CG717 — XQ2V3000 (Cont’d) Bank Pin Description 7 IO_L43P_7 7 IO_L43N_7 7 IO_L30P_7 7 IO_L30N_7 7 IO_L28P_7 7 IO_L28N_7 7 IO_L27P_7/VREF_7 7 IO_L27N_7 7 IO_L25P_7 7 IO_L25N_7 7 IO_L24P_7 7 IO_L24N_7 7 IO_L22P_7 7 IO_L22N_7 ...

Page 101

R Table 75: BG728 and CG717 — XQ2V3000 (Cont’d) Bank Pin Description 7 VCCO_7 7 VCCO_7 7 VCCO_7 7 VCCO_7 7 VCCO_7 7 VCCO_7 7 VCCO_7 NA CCLK NA PROG_B NA DONE HSWAP_EN ...

Page 102

R Table 75: BG728 and CG717 — XQ2V3000 (Cont’d) Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND ...

Page 103

R BG728 Standard BGA Package Specifications (1.27 mm pitch) X-Ref Target - Figure 53 Figure 53: BG728 Standard BGA Package Specifications DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs www.xilinx.com 103 ...

Page 104

R CG717 Ceramic Column Grid Array (CGA) Package Specifications (1.27 mm pitch) X-Ref Target - Figure 54 Figure 54: CG717 Ceramic CGA Package Specifications DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs www.xilinx.com 104 ...

Page 105

R EF957 Epoxy-Coated Flip-Chip BGA Package The XQ2V6000 QPro Virtex-II device is available in the EF957 epoxy-coated flip-chip BGA package. Pins definitions listed in Table 76 are identical to the commercial grade XC2V1000-FG456. Following this table are the Chip BGA ...

Page 106

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description 0 IO_L93N_0 0 IO_L93P_0 0 IO_L94N_0/VREF_0 0 IO_L94P_0 0 IO_L95N_0/GCLK7P 0 IO_L95P_0/GCLK6S 0 IO_L96N_0/GCLK5P 0 IO_L96P_0/GCLK4S 1 IO_L96N_1/GCLK3P 1 IO_L96P_1/GCLK2S 1 IO_L95N_1/GCLK1P 1 IO_L95P_1/GCLK0S 1 IO_L94N_1 1 IO_L94P_1/VREF_1 1 IO_L93N_1 ...

Page 107

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description 1 IO_L05P_1 1 IO_L04N_1 1 IO_L04P_1/VREF_1 1 IO_L03N_1/VRP_1 1 IO_L03P_1/VRN_1 1 IO_L02N_1 1 IO_L02P_1 1 IO_L01N_1 1 IO_L01P_1 2 IO_L01N_2 2 IO_L01P_2 2 IO_L02N_2/VRP_2 2 IO_L02P_2/VRN_2 2 IO_L03N_2 2 IO_L03P_2/VREF_2 ...

Page 108

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description 2 IO_L77N_2 2 IO_L77P_2 2 IO_L78N_2 2 IO_L78P_2 2 IO_L91N_2 2 IO_L91P_2 2 IO_L92N_2 2 IO_L92P_2 2 IO_L93N_2 2 IO_L93P_2/VREF_2 2 IO_L94N_2 2 IO_L94P_2 2 IO_L95N_2 2 IO_L95P_2 2 IO_L96N_2 ...

Page 109

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description 3 IO_L24P_3 3 IO_L23N_3 3 IO_L23P_3 3 IO_L22N_3 3 IO_L22P_3 3 IO_L21N_3/VREF_3 3 IO_L21P_3 3 IO_L20N_3 3 IO_L20P_3 3 IO_L19N_3 3 IO_L19P_3 3 IO_L06N_3 3 IO_L06P_3 3 IO_L05N_3 3 IO_L05P_3 ...

Page 110

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description 4 IO_L72N_4 4 IO_L72P_4 4 IO_L73N_4 4 IO_L73P_4 4 IO_L74N_4 4 IO_L74P_4 4 IO_L75N_4 4 IO_L75P_4/VREF_4 4 IO_L76N_4 4 IO_L76P_4 4 IO_L77N_4 4 IO_L77P_4 4 IO_L78N_4 4 IO_L78P_4 4 IO_L91N_4/VREF_4 ...

Page 111

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description 5 IO_L27P_5 5 IO_L26N_5 5 IO_L26P_5 5 IO_L25N_5 5 IO_L25P_5 5 IO_L24N_5 5 IO_L24P_5 5 IO_L23N_5 5 IO_L23P_5 5 IO_L22N_5 5 IO_L22P_5 5 IO_L21N_5/VREF_5 5 IO_L21P_5 5 IO_L20N_5 5 IO_L20P_5 ...

Page 112

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description 6 IO_L67P_6 6 IO_L67N_6 6 IO_L68P_6 6 IO_L68N_6 6 IO_L69P_6 6 IO_L69N_6/VREF_6 6 IO_L70P_6 6 IO_L70N_6 6 IO_L71P_6 6 IO_L71N_6 6 IO_L72P_6 6 IO_L72N_6 6 IO_L73P_6 6 IO_L73N_6 6 IO_L74P_6 ...

Page 113

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description 7 IO_L50N_7 7 IO_L49P_7 7 IO_L49N_7 7 IO_L48P_7 7 IO_L48N_7 7 IO_L47P_7 7 IO_L47N_7 7 IO_L46P_7 7 IO_L46N_7 7 IO_L45P_7/VREF_7 7 IO_L45N_7 7 IO_L44P_7 7 IO_L44N_7 7 IO_L43P_7 7 IO_L43N_7 ...

Page 114

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 ...

Page 115

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT ...

Page 116

R Table 76: EF957 — XQ2V6000 (Cont’d) Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND ...

Page 117

R EF957 Epoxy-Coated Flip-Chip BGA Package Specifications (1.00 mm pitch) X-Ref Target - Figure 55 Figure 55: EF957 Epoxy-Coated Flip-Chip BGA Package Specifications DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs www.xilinx.com 117 ...

Page 118

R CF1144 and EF1152 Ceramic Flip-Chip Fine-Pitch CGA Packages The XQ2V6000 QPro Virtex-II device is available in the CF1144 and FF1152 flip-chip fine-pitch CGA packages. Pins for the CF1144 package are the same as the FF1152, except for those pins ...

Page 119

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 0 IO_L73N_0 0 IO_L73P_0 0 IO_L74N_0 0 IO_L74P_0 0 IO_L75N_0 0 IO_L75P_0/VREF_0 0 IO_L76N_0 0 IO_L76P_0 0 IO_L77N_0 0 IO_L77P_0 0 IO_L78N_0 0 IO_L78P_0 0 IO_L79N_0 0 IO_L79P_0 ...

Page 120

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 1 IO_L67P_1 1 IO_L60N_1 1 IO_L60P_1 1 IO_L54N_1 1 IO_L54P_1 1 IO_L53N_1 1 IO_L53P_1 1 IO_L52N_1 1 IO_L52P_1 1 IO_L51N_1/VREF_1 1 IO_L51P_1 1 IO_L50N_1 1 IO_L50P_1 1 IO_L49N_1 ...

Page 121

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 2 IO_L29N_2 2 IO_L29P_2 2 IO_L30N_2 2 IO_L30P_2 2 IO_L43N_2 2 IO_L43P_2 2 IO_L44N_2 2 IO_L44P_2 2 IO_L45N_2 2 IO_L45P_2/VREF_2 2 IO_L46N_2 2 IO_L46P_2 2 IO_L47N_2 2 IO_L47P_2 ...

Page 122

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 3 IO_L93P_3 3 IO_L92N_3 3 IO_L92P_3 3 IO_L91N_3 3 IO_L91P_3 3 IO_L84N_3 3 IO_L84P_3 3 IO_L83N_3 3 IO_L83P_3 3 IO_L82N_3 3 IO_L82P_3 3 IO_L81N_3/VREF_3 3 IO_L81P_3 3 IO_L80N_3 ...

Page 123

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 3 IO_L21P_3 3 IO_L20N_3 3 IO_L20P_3 3 IO_L19N_3 3 IO_L19P_3 3 IO_L06N_3 3 IO_L06P_3 3 IO_L05N_3 3 IO_L05P_3 3 IO_L04N_3 3 IO_L04P_3 3 IO_L03N_3/VREF_3 3 IO_L03P_3 3 IO_L02N_3/VRP_3 ...

Page 124

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 4 IO_L75N_4 4 IO_L75P_4/VREF_4 4 IO_L76N_4 4 IO_L76P_4 4 IO_L77N_4 4 IO_L77P_4 4 IO_L78N_4 4 IO_L78P_4 4 IO_L79N_4 4 IO_L79P_4 4 IO_L80N_4 4 IO_L80P_4 4 IO_L81N_4 4 IO_L81P_4/VREF_4 ...

Page 125

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 5 IO_L54P_5 5 IO_L53N_5 5 IO_L53P_5 5 IO_L52N_5 5 IO_L52P_5 5 IO_L51N_5/VREF_5 5 IO_L51P_5 5 IO_L50N_5 5 IO_L50P_5 5 IO_L49N_5 5 IO_L49P_5 5 IO_L30N_5 5 IO_L30P_5 5 IO_L29N_5 ...

Page 126

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 6 IO_L43P_6 6 IO_L43N_6 6 IO_L44P_6 6 IO_L44N_6 6 IO_L45P_6 6 IO_L45N_6/VREF_6 6 IO_L46P_6 6 IO_L46N_6 6 IO_L47P_6 6 IO_L47N_6 6 IO_L48P_6 6 IO_L48N_6 6 IO_L49P_6 6 IO_L49N_6 ...

Page 127

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 7 IO_L91N_7 7 IO_L84P_7 7 IO_L84N_7 7 IO_L83P_7 7 IO_L83N_7 7 IO_L82P_7 7 IO_L82N_7 7 IO_L81P_7/VREF_7 7 IO_L81N_7 7 IO_L80P_7 7 IO_L80N_7 7 IO_L79P_7 7 IO_L79N_7 7 IO_L78P_7 ...

Page 128

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 7 IO_L19N_7 7 IO_L06P_7 7 IO_L06N_7 7 IO_L05P_7 7 IO_L05N_7 7 IO_L04P_7 7 IO_L04N_7 7 IO_L03P_7/VREF_7 7 IO_L03N_7 7 IO_L02P_7/VRN_7 7 IO_L02N_7/VRP_7 7 IO_L01P_7 7 IO_L01N_7 0 VCCO_0 ...

Page 129

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description 5 VCCO_5 5 VCCO_5 5 VCCO_5 5 VCCO_5 5 VCCO_5 5 VCCO_5 5 VCCO_5 5 VCCO_5 6 VCCO_6 6 VCCO_6 6 VCCO_6 6 VCCO_6 6 VCCO_6 6 VCCO_6 ...

Page 130

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT ...

Page 131

R Table 78: CF1152 and EF1144 — XQ2V6000 (Cont’d) Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND ...

Page 132

R CF1144 Ceramic Flip-Chip Fine-Pitch CGA Package Specifications (1.00 mm pitch) X-Ref Target - Figure 56 Figure 56: CF1144 Ceramic Flip-Chip Fine-Pitch CGA Package Specifications DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs www.xilinx.com 132 ...

Page 133

R EF1152 Epoxy-Coated Flip-Chip BGA Package Specifications (1.00 mm pitch) X-Ref Target - Figure 57 Figure 57: EF1152 Epoxy-Coated Flip-Chip BGA Package Specifications DS122 (v2.0) December 21, 2007 Product Specification QPro Virtex-II 1.5V Platform FPGAs www.xilinx.com 133 ...

Page 134

R References 1. UG002, Virtex-II Platform FPGA User Guide. 2. XAPP623, Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors. 3. XAPP689, Managing Ground Bounce in Large FPGAs. 4. DS031, Virtex-II Platform FPGAs. Revision History This section records the change history ...