XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 74

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for QPro Virtex-II source-
synchronous transmitter and receiver data-valid windows.
Table 65: Duty Cycle Distortion and Clock-Tree Skew
Table 66: Package Skew
Table 67: Sample Window
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
2.
Notes:
1.
2.
Notes:
1.
Duty Cycle Distortion
Clock Tree Skew
Package Skew
Sampling Error at Receiver Pins
♦ CLK0 and CLK180 DCM jitter
♦ Worst-case Duty-Cycle Distortion - T
♦ DCM accuracy (phase offset)
♦ DCM phase shift resolution.
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
T
T
I/O.
This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists
for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing
Analyzer tools to evaluate clock skew specific to your application.
These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball
(7.1 ps per mm).
Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
This parameter indicates the total sampling error of QPro Virtex-II DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include
These measurements do not include package or clock tree skew.
DCD_CLK0
DCD_CLK180
R
Description
Description
Description
(1)
applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O.
(2)
applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element in the
(1)
(1)
DCD_CLK180
T
T
T
DCD_CLK180
T
Symbol
Symbol
Symbol
DCD_CLK0
PKGSKEW
CKSKEW
T
SAMP
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XQ2V6000/CF1144
Device/Package
XQ2V1000
XQ2V3000
XQ2V6000
XQ2V1000
XQ2V3000
XQ2V6000
Device
Device
All
All
QPro Virtex-II 1.5V Platform FPGAs
140
100
500
500
500
500
50
80
-5
-5
Speed Grade
Speed Grade
Value
90
140
110
550
550
550
550
50
90
-4
-4
Units
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
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