SI1000-C-GM Silicon Laboratories Inc, SI1000-C-GM Datasheet - Page 211
![IC TXRX MCU + EZRADIOPRO](/photos/14/21/142131/42-qfn-series_sml.jpg)
SI1000-C-GM
Manufacturer Part Number
SI1000-C-GM
Description
IC TXRX MCU + EZRADIOPRO
Manufacturer
Silicon Laboratories Inc
Specifications of SI1000-C-GM
Package / Case
42-QFN
Frequency
240MHz ~ 960MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
General Purpose
Power - Output
20dBm
Sensitivity
-121dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
85mA
Data Interface
PCB, Surface Mount
Memory Size
64kB Flash, 4kB RAM
Antenna Connector
PCB, Surface Mount
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
240 MHz to 960 MHz
Interface Type
UART, SMBus, SPI, PCA
Output Power
20 dBm
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
4.1 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Protocol Supported
C2, SMBus
Core
8051
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
4352 B
Supply Current (max)
4.1 mA
Cpu Family
Si100x
Device Core
8051
Device Core Size
8b
Frequency (max)
25MHz
Total Internal Ram Size
4.25KB
# I/os (max)
22
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
18-chx10-bit
Instruction Set Architecture
CISC
Mounting
Surface Mount
Pin Count
42
Package Type
QFN EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1881-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI1000-C-GM
Manufacturer:
FSC
Quantity:
1 000
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21.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a Port I/O pin to each software selected digital function using the
fixed peripheral priority order shown in Figure 21.3. The registers XBR0, XBR1, and XBR2 defined in SFR
Definition 21.1, SFR Definition 21.2, and SFR Definition 21.3 are used to select digital functions in the
Crossbar. The Port pins available for assignment by the Crossbar include all Port pins (P0.0–P2.6) which
have their corresponding bit in PnSKIP set to 0.
From Figure 21.3, the highest priority peripheral is UART0. If UART0 is selected in the Crossbar (using the
XBRn registers), then P0.4 and P0.5 will be assigned to UART0. The next highest priority peripheral is
SPI1. If SPI1 is selected in the Crossbar, then P1.0–P1.2 will be assigned to SPI1. P1.3 will be assigned if
SPI1 is configured for 4-wire mode. The user should ensure that the pins to be assigned by the Crossbar
have their PnSKIP bits set to 0.
For all remaining digital functions selected in the Crossbar, starting at the top of Figure 21.3 going down,
the least-significant unskipped, unassigned Port pin(s) are assigned to that function. If a Port pin is already
assigned (e.g., UART0 or SPI1 pins), or if its PnSKIP bit is set to 1, then the Crossbar will skip over the pin
and find next available unskipped, unassigned Port pin. All Port pins used for analog functions, GPIO, or
dedicated digital functions such as the EMIF should have their PnSKIP bit set to 1.
Figure 21.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP =
0x00); Figure 21.4 shows the Crossbar Decoder priority with the External Oscillator pins (XTAL1 and
XTAL2) skipped (P0SKIP = 0x0C).
Notes:
Digital Function
External Interrupt 0
External Interrupt 1
Port Match
The Crossbar must be enabled (XBARE = 1) before any Port pin is used as a digital output. Port output
drivers are disabled while the Crossbar is disabled.
When SMBus is selected in the Crossbar, the pins associated with SDA and SCL will automatically be
forced into open-drain output mode regardless of the PnMDOUT setting.
SPI0 can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-
NSSMD0 bits in register SPI0CN. The NSS signal is only routed to a Port pin when 4-wire mode is
selected. When SPI0 is selected in the Crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout
of all digital functions lower in priority than SPI0.
For given XBRn, PnSKIP, and SPInCN register settings, one can determine the I/O pin-out of the
device using Figure 21.3 and Figure 21.4.
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions
Potentially Assignable Port Pins
Rev. 1.0
P0.0–P0.7
P0.0–P0.7
P0.0–P1.7
Si1000/1/2/3/4/5
P0MASK, P0MAT
P1MASK, P1MAT
SFR(s) used for
Assignment
IT01CF
IT01CF
211
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