SI1000-C-GM Silicon Laboratories Inc, SI1000-C-GM Datasheet
SI1000-C-GM
Specifications of SI1000-C-GM
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SI1000-C-GM Summary of contents
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... Pipelined instruction architecture; executes 70% of instruc- tions system clocks MIPS throughput with 25 MHz clock - Expanded interrupt handler - Memory 4352 bytes internal data RAM (256 + 4096 (Si1000/2/ (Si1001/3/5) Flash; In-system programmable in 1024-byte sectors—1024 bytes are reserved in the 64 kB devices ANALOG PERIPHERALS A 10-bit M 300 ksps U ...
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... Si1000/1/2/3/4/5 2 Rev. 1.0 ...
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... Comparator Inputs............................................................................................. 99 7.2. Comparator Outputs ........................................................................................ 100 7.3. Comparator Response Time ........................................................................... 101 7.4. Comparator Hysteresis.................................................................................... 101 7.5. Comparator Register Descriptions .................................................................. 102 7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 106 8. CIP-51 Microcontroller........................................................................................... 109 8.1. Performance .................................................................................................... 109 8.2. Programming and Debugging Support ............................................................ 110 Si1000/1/2/3/4/5 Rev. 1.0 3 ...
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... Si1000/1/2/3/4/5 8.3. Instruction Set.................................................................................................. 110 8.4. CIP-51 Register Descriptions .......................................................................... 115 9. Memory Organization ............................................................................................ 118 9.1. Program Memory............................................................................................. 119 9.2. Data Memory ................................................................................................... 119 10. On-Chip XRAM ..................................................................................................... 121 10.1. Accessing XRAM........................................................................................... 121 10.2. Special Function Registers............................................................................ 122 11. Special Function Registers................................................................................. 123 11.1. SFR Paging ................................................................................................... 124 12 ...
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... Serial Clock Phase and Polarity .................................................................... 232 22.6. SPI Special Function Registers ..................................................................... 233 ® 23. EZRadioPRO 240–960 MHz Transceiver.......................................................... 239 23.1. EZRadioPRO Operating Modes .................................................................... 240 23.2. Interrupts ...................................................................................................... 243 23.3. System Timing............................................................................................... 244 23.4. Modulation Options........................................................................................ 251 23.5. Internal Functional Blocks ............................................................................. 256 Si1000/1/2/3/4/5 Rev. 1.0 5 ...
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... Si1000/1/2/3/4/5 23.6. Data Handling and Packet Handler ............................................................... 261 23.7. RX Modem Configuration .............................................................................. 269 23.8. Auxiliary Functions ........................................................................................ 269 23.9. Reference Design.......................................................................................... 280 23.10. Application Notes and Reference Designs .................................................. 283 23.11. Customer Support ....................................................................................... 283 23.12. Register Table and Descriptions ................................................................. 284 23.13. Required Changes to Default Register Values............................................ 286 24 ...
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... SFR Definition 13.3. FLSCL: Flash Scale ................................................................... 150 SFR Definition 13.4. FLWR: Flash Write Only ............................................................ 150 SFR Definition 14.1. PMU0CF: Power Management Unit Configuration SFR Definition 14.2. PCON: Power Management Control Register ........................... 157 SFR Definition 15.1. CRC0CN: CRC0 Control ........................................................... 161 Si1000/1/2/3/4/5 1,2 Rev. 1.0 ................ 156 7 ...
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... Si1000/1/2/3/4/5 SFR Definition 15.2. CRC0IN: CRC0 Data Input ........................................................ 162 SFR Definition 15.3. CRC0DAT: CRC0 Data Output .................................................. 162 SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control ...................................... 163 SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 163 SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 164 SFR Definition 16 ...
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... SFR Definition 28.8. PCA0CPHn: PCA Capture Module High Byte ........................... 370 C2 Register Definition 29.1. C2ADD: C2 Address ...................................................... 371 C2 Register Definition 29.2. DEVICEID: C2 Device ID ............................................... 372 C2 Register Definition 29.3. REVID: C2 Revision ID .................................................. 372 C2 Register Definition 29.4. FPCTL: C2 Flash Programming Control ........................ 373 C2 Register Definition 29.5. FPDAT: C2 Flash Programming Data ............................ 373 Si1000/1/2/3/4/5 Rev. 1.0 9 ...
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... Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 25 Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 26 Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 26 Figure 3.1. Si1000/1/2/3 Pinout Diagram (Top View) .............................................. 32 Figure 3.2. Si1004/5 Pinout Diagram (Top View) .................................................... 33 Figure 3.3. QFN-42 Package Drawing .................................................................... 34 Figure 3.4. Typical QFN-42 Landing Diagram ......................................................... 36 Figure 3 ...
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... Figure 7.3. Comparator Hysteresis Plot ................................................................ 101 Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 106 Figure 8.1. CIP-51 Block Diagram ......................................................................... 109 Figure 9.1. Si1000/1/2/3/4/5 Memory Map ............................................................ 118 Figure 9.2. Flash Program Memory Map ............................................................... 119 Figure 13.1. Flash Program Memory Map ............................................................. 143 Figure 14.1. Si1000/1/2/3/4/5 Power Distribution .................................................. 152 Figure 15 ...
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... Figure 23.24. Low Duty Cycle Mode ..................................................................... 278 Figure 23.25. RSSI Value vs. Input Power ............................................................ 280 Figure 23.26. Si1002 Split RF TX/RX Direct-Tie Reference Design—Schematic . 281 Figure 23.27. Si1000 Switch Matching Reference Design—Schematic ................ 282 Figure 24.1. SMBus Block Diagram ...................................................................... 287 Figure 24.2. Typical SMBus Configuration ............................................................ 288 Figure 24 ...
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... Figure 28.8. PCA 8-Bit PWM Mode Diagram ........................................................ 360 Figure 28.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 361 Figure 28.10. PCA 16-Bit PWM Mode ................................................................... 362 Figure 28.11. PCA Module 5 with Watchdog Timer Enabled ................................ 363 Figure 29.1. Typical C2 Pin Sharing ...................................................................... 374 Si1000/1/2/3/4/5 Rev. 1.0 13 ...
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... Si1000/1/2/3/4/5 List of Tables Table 2.1. Product Selection Guide ......................................................................... 27 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 .................................................. 28 Table 3.2. QFN-42 Package Dimensions ................................................................ 35 Table 3.3. PCB Land Pattern ................................................................................... 39 Table 4.1. Absolute Maximum Ratings .................................................................... 40 Table 4.2. Global Electrical Characteristics ............................................................. 41 Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 51 Table 4 ...
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... Table 26.1. SPI Slave Timing Parameters ............................................................ 329 Table 27.1. Timer 0 Running Modes ..................................................................... 332 Table 28.1. PCA Timebase Input Options ............................................................. 353 Table 28.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules ................................................................ 355 Table 28.3. Watchdog Timer Timeout Intervals1 ................................................... 364 Si1000/1/2/3/4/5 Rev. 1.0 15 ...
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... Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals The Si1000/1/2/3/4/5 are available in a 42-pin QFN package (lead-free and RoHS compliant). See Table 2.1 for ordering information. Block dia- grams are included in Figure 1.1 through Figure 1.6. The transceiver's extremely low receive sensitivity (– ...
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... MHz Oscillator External P0.2/XTAL1 Oscillator P0.3/XTAL2 Circuit XTAL3 SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.1. Si1000 Block Diagram CIP-51 8051 Power On Controller Core Reset/PMU 32k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 4096 Byte XRAM ...
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... Si1000/1/2/3/4/5 CIP-51 8051 Power On Controller Core Reset/PMU 64k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 4096 Byte XRAM Hardware C2D VDD VREG GND Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator External P0.2/XTAL1 Oscillator P0.3/XTAL2 ...
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... Low Power Converter 20 MHz Oscillator GND External XTAL1 Oscillator XTAL2 Circuit XTAL3 SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.6. Si1005 Block Diagram Si1000/1/2/3/4/5 Analog Peripherals RF XCVR (240-960 MHz) 6-bit IREF0 IREF PA External Internal VREF VREF AGC VDD VREF A 10-bit Temp ...
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... Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example Supply Voltage C6 C7 100 p 100 n TR & ANT-DIV L3 L2 Switch Figure 1.8. Si1000/1 Antenna Diversity Application Example 30MHz 1u L1 VDD_RF VDD_MCU VDD_DIG TX Px.x C1 RFp Si100x RXn Programmable load capacitors for X1 are integrated. L1-L6 and C1-C5 values depend on frequency band, antenna impedance, output power and supply voltage range ...
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... With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. 1.2.3. Additional Features The Si1000/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51, allowing numerous analog and digital peripherals to interrupt the controller ...
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... Si1000/1/2/3/4/5 1.3. Port Input/Output Digital and analog resources are available through 19 (Si1000/1/2/ (Si1004/5) I/O pins. Three addi- tional GPIO pins are available through the EZRadioPRO peripheral. Port pins are organized as three byte- wide ports. Port pins P0.0–P2.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO) ...
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... Serial Ports The Si1000/1/2/3/4/5 family includes an SMBus/I configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. There is also a dedicated EZRadioPRO Serial Interface (SPI1) to allow communication with the EZRadioPRO peripheral ...
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... SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode Si1000/1/2/3/4/5 devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with inte- grated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention ...
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... Figure 1.12. ADC0 Multiplexer Block Diagram 1.7. Programmable Current Reference (IREF0) Si1000/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two out- put current settings: low power mode and high current mode. The maximum current output in low power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps). ...
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... Si1000/1/2/3/4/5 CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer Px.x CP0 + Px.x Px.x CP0 - Px.x Figure 1.13. Comparator 0 Functional Block Diagram CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 Analog Input Multiplexer Px.x CP1 + Px.x Px.x CP1 - Px.x Figure 1 ...
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... Ordering Information Table 2.1. Product Selection Guide Si1000-C- 4352 P Si1001-C- 4352 P Si1002-C- 4352 P Si1003-C- 4352 P Si1004-C- 4352 P Si1005-C- 4352 Rev. 1.0 Si1000/1/2/3/4/5 +20 dBm 1.8 P QFN-42 +20 dBm 1.8 P QFN-42 +13 dBm 1.8 P QFN-42 +13 dBm 1.8 P QFN-42 +13 dBm 0.9 P QFN-42 +13 dBm 0.9 P QFN-42 27 ...
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... Si1000/1/2/3/4/5 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 Name Pin Number Si1000/1 Si1004/5 Si1002/3 VDD_MCU 38 — GND_MCU 37 — — VBAT 41 GND — 38 VBAT- DCEN — 40 VDD_MCU / — 39 DC+ GND_MCU — 37 DC– VDD_RF 16 16 VDD_DIG 28 28 VR_DIG ...
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... Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Type Si1000/1 Si1004/5 Si1002/3 RST I/O C2CK D I/O P2. I/O C2D D I/O XTAL3 XTAL4 Out P0 I REF A Out P0 I AGND P0 I XTAL1 P0 I Out XTAL2 Si1000/1/2/3/4/5 Description Device Reset. Open-drain output of internal POR or V monitor. An external source can initiate a system reset by driving this pin low for at least 15 µ ...
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... Si1000/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Si1000/1 Si1004/5 Si1002 CNVSTR P0 IREF0 P2.4 3 — P2.5 2 — P2.6 41 — 30 Type Description D I/O or Port 0.4. See Port I/O section for a complete description Out UART TX Pin. See Port I/O section. ...
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... Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Type Si1000/1 Si1004/5 Si1002/3 GPIO_0 I I/O GPIO_1 I I/O GPIO_2 I I/O nIRQ XOUT XIN 14, 20, 14, 20 SDN RXp RXn ANT_A Si1000/1/2/3/4/5 Description General Purpose I/O controlled by the EZRadioPRO periph- eral. May be configured through the EZRadioPRO registers ...
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... Si1000/1/2/3/4/5 XTAL3 1 P2.5 2 P2.4 3 P2.3 4 P2.2 5 P2.1 6 P2.0 7 P1 P1.5 nIRQ 11 XOUT 12 XIN 13 N.C. 14 Figure 3.1. Si1000/1/2/3 Pinout Diagram (Top View) 32 GND_MCU Si1000/1/2/3 Top View GND_RF Rev. 1.0 35 P0.1/AGND 34 P0.2/XTAL1 33 P0.3/XTAL2 32 P0.4/TX 31 P0.5/RX 30 P0.6/CNVSTR P0.7/IREF0 29 VDD_DIG 28 VR_DIG 27 26 GPIO_2 25 GPIO_1 ...
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... P2.7/C2D 1 XTAL4 2 XTAL3 3 P2.3 4 P2.2 5 P2.1 6 P2.0 7 P1.7 8 P1.6 9 P1.5 10 nIRQ 11 XOUT 12 XIN 13 N.C. 14 Figure 3.2. Si1004/5 Pinout Diagram (Top View) Si1000/1/2/3/4/5 GND_M CU Si1004/5 Top View GND_RF Rev. 1.0 35 P0.1/AGND 34 P0.2/XTAL1 P0.3/XTAL2 33 P0.4/TX 32 P0.5/ P0.6/CNVSTR 29 P0.7/IREF0 28 VDD_DIG 27 VR_DIG GPIO_2 26 25 GPIO_1 24 ...
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... Si1000/1/2/3/4/5 Figure 3.3. QFN-42 Package Drawing 34 Rev. 1.0 ...
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... All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 4. All pitches other than P1, P2 are represented by e. Si1000/1/2/3/4/5 Dimension Min Typ F 0.07 REF G 1 ...
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... Si1000/1/2/3/4/5 Figure 3.4. Typical QFN-42 Landing Diagram 36 Rev. 1.0 ...
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... Figure 3.5. VIA Placement and Keepout Region Si1000/1/2/3/4/5 Rev. 1.0 37 ...
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... Si1000/1/2/3/4/5 Figure 3.6. Typical PCB Stencil Diagram 38 Rev. 1.0 ...
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... A 3x3 array of 0.8 mm square openings on 1.0 mm pitch should be used for the lower center ground pad. 5. Card Assembly A No-Clean, Type-3 solder paste is recommended. 1. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 2. Table 3.3. PCB Land Pattern Rev. 1.0 Si1000/1/2/3/4/5 Value 4.75 0.95 0.30 7.00 0.30 0.70 0.50 > ...
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... Si1000/1/2/3/4/5 4. Electrical Characteristics In sections 4.1 and 4.2, , “V ” refers to the VDD_MCU supply voltage on Si1000/1/2/3 devices and to the DD VDD_MCU/DC+ supply voltage on Si1004/5 devices. The ADC, Comparator, and Port I/O specifications in these two sections do not apply to the EZRadioPRO peripheral. In sections 4.3 and 4.4, “V ” ...
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... Minimum RAM Data VDD (not in Sleep Mode) VBAT (in Sleep Mode) 1 Retention Voltage 2 SYSCLK (System Clock) T (SYSCLK High Time) SYSH T (SYSCLK Low Time) SYSL Specified Operating Temperature Range Si1000/1/2/3/4/5 Conditions Min Typ 0.9 1.2 1.8 2.4 1.8 1.9 1.8 2.4 — 1.4 — ...
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... Si1000/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) ...
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... Mode, SmaRTClock 3 running (includes SmaRTClock oscillator and brownout detector) 8 1 °C Digital Supply Current 3 °C (Sleep Mode) 3 °C 1 °C 3 °C 3 °C (includes brownout detector) Si1000/1/2/3/4/5 Conditions V = 1.8–3.6 V, two-cell mode DD C ° C ° C ° C ° C ° C ° Rev. 1.0 ...
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... Si1000/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Notes: 1. Based on device characterization data; Not production tested. ...
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... Figure 4.1. Active Mode Current (External CMOS Clock) Si1000/1/2/3/4/5 F > 10 MHz Oneshot Bypassed 200 µA/MHz 215 µA/MHz Frequency (MHz) Rev. 1.0 < 170 µA/MHz 45 ...
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... Si1000/1/2/3/4/5 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 ...
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... Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC Si1000/1/2/3/4/5 Load Current (mA) Rev. 1.0 47 ...
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... Si1000/1/2/3/4/5 Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC Load current (mA) Rev. 1.0 ...
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... Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC Si1000/1/2/3/4/5 Load current (mA) Rev. 1.0 49 ...
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... Si1000/1/2/3/4/5 Figure 4.6. Typical One-Cell Suspend Mode Current 50 Rev. 1.0 ...
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... V – 0.6 DD 0.7 x VDD — — 1.8 V — 3.6 V — DD Rev. 1.0 Si1000/1/2/3/4/5 Typ Max Units V — — — — See Chart — — — — See Chart — V — 0.6 — 0.1 See Chart — ...
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... Si1000/1/2/3/4/5 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 Figure 4.7. Typical VOH Curves, 1.8–3 Typical VOH (High Drive Mode Load Current (mA) Typical VOH (Low Drive Mode Load Current (mA) Rev. 1.0 VDD = 3.6V VDD = 3 ...
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... Typical VOH (Low Drive Mode) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0 Load Current (mA) Figure 4.8. Typical VOH Curves, 0.9–1.8 V Rev. 1.0 Si1000/1/2/3/4/5 VDD = 1.8V VDD = 1.5V VDD = 1.2V VDD = 0. VDD = 1.8V VDD = 1.5V VDD = 1.2V VDD = 0. ...
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... Si1000/1/2/3/4/5 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 1.8 1.5 1.2 0.9 0.6 0 Figure 4.9. Typical VOL Curves, 1.8–3 Typical VOL (High Drive Mode) VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V -60 -50 -40 -30 -20 -10 Load Current (mA) Typical VOL (Low Drive Mode) VDD = 3 ...
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... Load Current (mA) Typical VOL (Low Drive Mode) 1.8 1.5 1.2 0.9 0.6 0 Load Current (mA) Figure 4.10. Typical VOL Curves, 1.8–3.6 V Rev. 1.0 Si1000/1/2/3/4/5 VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V -20 -10 0 VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1. ...
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... Si1000/1/2/3/4/5 0.5 0.4 0.3 0.2 0 0.5 0.4 0.3 VDD = 1.8V 0.2 VDD = 1.5V VDD = 1.2V 0.1 VDD = 0. Figure 4.11. Typical VOL Curves, 0.9–1 Typical VOL (High Drive Mode) VDD = 1.8V VDD = 1.5V VDD = 1.2V VDD = 0. Load Current (mA) Typical VOL (Low Drive Mode) ...
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... V DD RST = 0.0 V, VDD = 1.8 V RST = 0.0 V, VDD = 3.6 V Early Warning Reset Trigger V Ramp from 0–0 Rising) DD Falling) DD Rising reset initiation source and code Rev. 1.0 Si1000/1/2/3/4/5 Min Typ Max Units — — 0.6 V – 0.6 — — — — — ...
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... Write Cycle Time Note: 1024 bytes at addresses 0xFC00 to 0xFFFF are reserved. 58 Conditions Min 2 Low power oscillator — Precision oscillator — Two-cell mode — One-cell mode — Conditions Min Si1000/2/4 65536* Si1001/3/5 32768 1024 Rev. 1.0 Typ Max Units — 3 SYSCLKs 400 — ...
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... Using factory-calibrated settings Parameter Oscillator Frequency Oscillator Supply Current No separate bias current (from *Note: Does not include clock divider or clock tree supply current. Si1000/1/2/3/4/5 Conditions Min –40 to +85 ° 1.8–3 — of 90–100 µA Conditions Min – ...
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... Si1000/1/2/3/4/5 Table 4.9. ADC0 Electrical Characteristics V = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Dynamic performance (10 kHz sine-wave single-ended input below Full Scale, 300 ksps) Signal-to-Noise Plus Distortion Signal-to-Distortion Spurious-Free Dynamic Range ...
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... V = 1.8–3 — — — bypass, settling to 0.5 LSB — 0.5 LSB — — 0 — 3.0 V Rev. 1.0 Si1000/1/2/3/4/5 Typ Max Units ±1 — °C 3.40 — mV/°C 40 — µV/°C 1025 — — mV — ...
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... Si1000/1/2/3/4/5 Table 4.12. IREF0 Electrical Characteristics V = 1 +85 °C, unless otherwise specified. – DD Parameter Static Performance Resolution Output Compliance Range High Current Mode, Source Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error* High Current Mode, Source Absolute Current Error Dynamic Performance ...
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... Input Bias Current Input Offset Voltage Power Supply Power Supply Rejection Power-up Time Supply Current at DC Note: Vcm is the common-mode voltage on CP0+ and CP0–. Si1000/1/2/3/4/5 Conditions Min CP0+ – CP0– = 100 mV — CP0+ – CP0– = –100 mV — CP0+ – CP0– = 100 mV — ...
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... Si1000/1/2/3/4/5 Table 4.13. Comparator Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Hysteresis Mode 0 Hysteresis 1 Hysteresis 2 Hysteresis 3 Hysteresis 4 Mode 1 Hysteresis 1 Hysteresis 2 Hysteresis 3 Hysteresis 4 Mode 2 Hysteresis 1 Hysteresis 2 Hysteresis 3 Hysteresis 4 Mode 3 Hysteresis 1 Hysteresis 2 Hysteresis 3 Hysteresis 4 Note: Vcm is the common-mode voltage on CP0+ and CP0–. ...
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... Target Output = 2.0 V Target Output = 2.1 V Target Output = 2.4 V Target Output = 2.7 V Target Output = 3.0 V Target Output = 3.3 V from VBAT supply from VDD/DC+ supply Conditions Min 1.8 — Rev. 1.0 Si1000/1/2/3/4/5 Min Typ Max Units 0.9 — 1.8 V 500 680 900 nH 250 — ...
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... TUNE Mode Current I Tune RX Mode Current Mode Current I TX_+20 —Si1000/1 TX Mode Current I TX_+13 —Si1002/3 I TX_+1 Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the "Production Test Conditions" section on page 73. ...
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... XOSC running to any frequency. Including VCO Calibration. Integrated over 250 kHz band- width (500 Hz lower bound of integration) kHz ) F = 100 kHz MHz MHz Rev. 1.0 Si1000/1/2/3/4/5 Min Typ Max Units 240 — 960 MHz — 156.25 — ...
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... Si1000/1/2/3/4/5 Table 4.18. Receiver AC Electrical Characteristics Parameter Symbol RX Frequence Range Sensitivity P RX_2 P RX_40 P RX_100 P RX_125 P RX_OOK 3 RX Channel Bandwidth BW BER Variation vs Power P RX_RES 3 Level 3 LNA Input Impedance R IN-RX (Unmatched—measured differentially across RX input pins) RSSI Resolution RES RSSI 3 1-Ch Offset Selectivity ...
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... All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the "Production Test Conditions" section on page 73. 2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on page 73. 3. Output power is dependent on matching components, board layout, and is measured at the pin. Si1000/1/2/3/4/5 1 Conditions Min 240 ...
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... Si1000/1/2/3/4/5 Table 4.20. Auxiliary Block Specifications Parameter Symbol Temperature Sensor Accuracy Temperature Sensor Sensitivity Low Battery Detector LBD 2 Resolution Low Battery Detector LBD 2 Conversion Time Microcontroller Clock Output Frequency General Purpose ADC ADC 2 Resolution General Purpose ADC Bit ...
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... L V 0<V < DRV<1:0>=LL DRV<1:0>=LH DRV<1:0>=HL DRV<1:0>=HH I < I source Omax V =1 < I sink, OL Omax V =1 Rev. 1.0 Si1000/1/2/3/4/5 Min Typ Max Units — — — — — — – 0.6 — — — 0.6 V –100 — 100 nA – 0.6 — — ...
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... Si1000/1/2/3/4/5 Table 4.23. Absolute Maximum Ratings Parameter V to GND DD Instantaneous V to GND on TX Output Pin RF-peak Sustained V to GND on TX Output Pin RF-peak Voltage on Digital Control Inputs Voltage on Analog Inputs RX Input Power Operating Ambient Temperature Range T Thermal Impedance JA Junction Temperature T ...
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... +1.8 to +3.6 VDC DD Using 4432, 4431, or 4430 DKDB1 reference design or production test schematic All RF input and output levels referred to the pins of the Si100x (not the RF module) Si1000/1/2/3/4 MHz, centered around 0.8 VDC PP Rev. 1.0 73 ...
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... SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode The ADC0 on the Si1000/1/2/3/4 300 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention ...
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... Result V x 1023/1024 0x07F7 REF V x 512/1024 0x0400 REF V x 511/1024 0x03FE REF 0 0x0000 Si1000/1/2/3/4/5 Left-Justified ADC0H:ADC0L (AD0SJST = 100) 0xFFC0 0x8000 0x4000 0x0000 n samples is equivalent to left-shifting by n bit positions when all Repeat Count = 16 Repeat Count = 64 0x3FF0 0xFFC0 0x2000 0x8000 0x1FF0 ...
Page 76
... Si1000/1/2/3/4/5 5.2. Modes of Operation ADC0 has a maximum conversion speed of 300 ksps. The ADC0 conversion clock (SARCLK divided version of the system clock when Burst Mode is disabled (BURSTEN = 0 divided version of the low power oscillator when Burst Mode is enabled (BURSEN = 1). The clock divide value is determined by the AD0SC bits in the ADC0CF register ...
Page 77
... Timer 1, Timer 3 Overflow (AD0CM[2:0]=000, 001,010 011, 101) SAR Clocks Low Power AD0TM=1 or Convert SAR Clocks Track or AD0TM=0 Convert Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0) Si1000/1/2/3/4 Track Convert Convert Track Convert Convert Rev. 1.0 Low Power Mode ...
Page 78
... Si1000/1/2/3/4/5 5.2.3. Burst Mode Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver- sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 16, 32 using an internal Burst Mode clock (approximately 20 MHz), then re-enters a low power state. Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a low power state within a single system clock cycle, even if the system clock is slow (e ...
Page 79
... AMUX0 resistance and any external source resistance. R TOTAL n is the ADC resolution in bits (10). P0.x Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.9 for details. Figure 5.4. ADC0 Equivalent Input Circuits Si1000/1/2/3/4/5 . See Table 4.9 for ADC0 minimum settling time require- MUX n 2 ...
Page 80
... Si1000/1/2/3/4/5 5.2.5. Gain Setting The ADC has gain settings of 1x and 0.5x mode, the full scale reading of the ADC is determined directly 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is V REF The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small V age measure input voltages that are between V trolled by the AMP0GN bit in register ADC0CF ...
Page 81
... Specifies the ADC0 start of conversion source. 000: ADC0 conversion initiated on write AD0BUSY. 001: ADC0 conversion initiated on overflow of Timer 0. 010: ADC0 conversion initiated on overflow of Timer 2. 011: ADC0 conversion initiated on overflow of Timer 3. 1xx: ADC0 conversion initiated on rising edge of CNVSTR AD0BUSY AD0WINT R Function Rev. 1.0 Si1000/1/2/3/4 ADC0CM R ...
Page 82
... Si1000/1/2/3/4/5 SFR Definition 5.2. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Page = 0x0; SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider. SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC[4:0]. SAR Conversion clock requirements are given in Table 4 ...
Page 83
... This bit field must be set to 000 if Burst Mode is disabled. 000: Perform and Accumulate 1 conversion. 001: Perform and Accumulate 4 conversions. 010: Perform and Accumulate 8 conversions. 011: Perform and Accumulate 16 conversions. 100: Perform and Accumulate 32 conversions. 101: Perform and Accumulate 64 conversions. All remaining bit combinations are reserved. Si1000/1/2/3/4 AD0SJST R ...
Page 84
... Si1000/1/2/3/4/5 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time Bit 7 6 Name Reserved R R Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xBA Bit Name 7 Reserved Read = 0b; Must write 0b. 6:4 Unused Read = 0000b; Write = Don’t Care. 3:0 AD0PWR[3:0] ADC0 Burst Mode Power-Up Time. ...
Page 85
... The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first conversion should be met by the Burst Mode Power-Up Time AD0TK[5:0] R Function Ttrack – ---------------- - 1 – 50ns 50ns 64 AD0TK – Rev. 1.0 Si1000/1/2/3/4 ...
Page 86
... Si1000/1/2/3/4/5 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBE Bit Name Description 7:0 ADC0[15:8] ADC0 Data Word High Byte. Note: If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register should not be written when the SYNC bit is set to 1 ...
Page 87
... Name Type 1 1 Reset SFR Page = 0x0; SFR Address = 0xC3 Bit Name 7:0 AD0GT[7:0] ADC0 Greater-Than Low Byte. Least Significant Byte of the 16-bit Greater-Than window compare register. Note: In 8-bit mode, this register should be set to 0x00. Si1000/1/2/3/4 AD0GT[15:8] R Function AD0GT[7:0] R/W ...
Page 88
... Si1000/1/2/3/4/5 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xC6 Bit Name 7:0 AD0LT[15:8] ADC0 Less-Than High Byte. Most Significant Byte of the 16-bit Less-Than window compare register. SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ...
Page 89
... AD0WINT not affected 0x0000 0 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data 5.4.2. ADC0 Specifications See “4. Electrical Characteristics” on page 40 for a detailed listing of ADC0 specifications. Si1000/1/2/3/4/5 ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF 0x0081 VREF x (128/1024) 0x0080 ...
Page 90
... Si1000/1/2/3/4/5 5.5. ADC0 Analog Multiplexer ADC0 on Si1000/1/2/3/4/5 has an analog multiplexer, referred to as AMUX0. AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the positive input: Port I/O pins, the on-chip temperature sensor, Regulated Digital Supply Voltage (Output of VREG0), VDD_MCU Supply, or the positive input may be connected to GND ...
Page 91
... P0.4 00101: P0.5 00110: P0.6 00111: P0.7 01000: Reserved. 01001: Reserved. 01010: Reserved. 01011: Reserved. 01100: Reserved. 01101: P1.5 01110: P1.6 01111: P1.7 Si1000/1/2/3/4 AD0MX R R/W R/W R Function 10000: 10001: 10010: 10011: 10100: 10101: 10110: 10111: 11000: 11001: 11010: 11011: ...
Page 92
... Si1000/1/2/3/4/5 5.6. Temperature Sensor An on-chip temperature sensor is included on the Si1000/1/2/3/4/5 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should select the temperature sensor. The temperature sensor transfer function is shown in Figure 5 ...
Page 93
... SFR registers TOFFH and TOFFL, shown in SFR Definition 5.13 and SFR Definition 5.14. 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.9. Temperature Sensor Error with 1-Point Calibration (V Si1000/1/2/3/4/5 40.00 0.00 60.00 20.00 Temperature (degrees C) Rev. 1.0 5.00 4.00 3.00 2.00 1.00 0.00 80.00 -1.00 -2 ...
Page 94
... Si1000/1/2/3/4/5 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte Bit 7 6 Name R R Type Varies Varies Varies Reset SFR Page = 0xF; SFR Address = 0x86 Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Bits. Most Significant Bits of the 10-bit temperature sensor offset measurement. ...
Page 95
... External Voltage References To use an external voltage reference, REFSL[1:0] should be set to 00 and the internal 1.68 V precision ref- erence should be disabled by setting REFOE to 0. Bypass capacitors should be added as recommended by the manufacturer of the external voltage reference. Si1000/1/2/3/4/5 VDD_MCU and the external ground reference REF ...
Page 96
... Si1000/1/2/3/4/5 5.9. Internal Voltage References For applications requiring the maximum number of port I/O pins, or very short VREF turn-on time, the 1.65 V high-speed reference will be the best internal reference option to choose. The high speed internal reference is selected by setting REFSL[1:0] to 11. When selected, the high speed internal reference will be automatically enabled/disabled on an as-needed basis by ADC0 ...
Page 97
... Internal 1.68 V Precision Voltage Reference disabled and not connected to P0.0/VREF. 1: Internal 1.68 V Precision Voltage Reference enabled and connected to P0.0/VREF. 5.12. Voltage Reference Electrical Specifications See Table 4.11 on page 61 for detailed Voltage Reference Electrical Specifications REFSL TEMPE R/W R/W R Function Rev. 1.0 Si1000/1/2/3/4 REFOE R ...
Page 98
... Si1000/1/2/3/4/5 6. Programmable Current Reference (IREF0) Si1000/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two out- put current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power Mode is 63 µA (1 µA steps) and the maximum current output in High Current Mode is 504 µA (8 µA steps). ...
Page 99
... Comparators Si1000/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate identi- cally, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources chapter and the Power Management chapter for details on reset sources and low power mode wake-up sources, respectively ...
Page 100
... Si1000/1/2/3/4/5 7.2. Comparator Outputs When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the voltage at the negative input. When disabled, the comparator output is a logic 0. The comparator output is synchronized with the system clock as shown in Figure 7.2. The synchronous “latched” output (CP0, CP1) can be polled in software (CPnOUT bit), used as an interrupt source, or routed to a Port pin through the Crossbar ...
Page 101
... CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 7.3. Comparator Hysteresis Plot Si1000/1/2/3/4/5 OUT Negative Hysteresis Disabled Negative Hysteresis Maximum Positive Hysteresis Rev. 1.0 Negative Hysteresis Voltage (Programmed by CP0HYN Bits) Maximum 101 ...
Page 102
... Si1000/1/2/3/4/5 7.5. Comparator Register Descriptions The SFRs used to enable and configure the comparators are described in the following register descrip- tions. A Comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used. From an enabled state, a comparator can be disabled and placed in a low power state by clearing the CPnEN bit to logic 0 ...
Page 103
... CP0MD[1:0] Comparator0 Mode Select. These bits affect the response time and power consumption for Comparator0. 00: Mode 0 (Fastest Response Time, Highest Power Consumption) 01: Mode 1 10: Mode 2 11: Mode 3 (Slowest Response Time, Lowest Power Consumption CP0FIE R/W R Function Rev. 1.0 Si1000/1/2/3/4 CP0MD[1: 103 ...
Page 104
... Si1000/1/2/3/4/5 SFR Definition 7.3. CPT1CN: Comparator 1 Control Bit 7 6 CP1EN CP1OUT CP1RIF Name R/W R Type 0 0 Reset SFR Page= 0x0; SFR Address = 0x9A Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. 6 CP1OUT Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. ...
Page 105
... CP1MD[1:0] Comparator1 Mode Select These bits affect the response time and power consumption for Comparator1. 00: Mode 0 (Fastest Response Time, Highest Power Consumption) 01: Mode 1 10: Mode 2 11: Mode 3 (Slowest Response Time, Lowest Power Consumption CP1FIE R/W R Function Rev. 1.0 Si1000/1/2/3/4 CP1MD[1: 105 ...
Page 106
... Si1000/1/2/3/4/5 7.6. Comparator0 and Comparator1 Analog Multiplexers Comparator0 and Comparator1 on Si1000/1/2/3/4/5 devices have analog input multiplexers to connect Port I/O pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input multiplexers for Comparator0 and CP1+/CP1- are the positive and negative input multiplexers for Comparator1 ...
Page 107
... Function 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Rev. 1.0 Si1000/1/2/3/4 CMX0P[3:0] R/W R/W R P2.1 P2.3 P2.5 Reserved Capacitive Touch Sense Compare VDD_MCU divided by 2 Digital Supply Voltage Ground P2.0 P2 ...
Page 108
... Si1000/1/2/3/4/5 SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select Bit 7 6 CMX1N[3:0] Name R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9E Bit Name 7:4 CMX1N Comparator1 Negative Input Selection. Selects the negative input channel for Comparator1. 0000: P0.1 0001: P0 ...
Page 109
... ALU REGISTER DATA BUS SFR_ADDRESS BUFFER D8 SFR_CONTROL SFR BUS D8 SFR_WRITE_DATA DATA POINTER D8 INTERFACE SFR_READ_DATA PC INCREMENTER MEM_ADDRESS D8 PROGRAM COUNTER (PC) MEM_CONTROL MEMORY PRGM. ADDRESS REG. MEM_WRITE_DATA A16 INTERFACE MEM_READ_DATA PIPELINE D8 CONTROL LOGIC SYSTEM_IRQs INTERRUPT INTERFACE EMULATION_IRQ D8 POWER CONTROL D8 REGISTER Rev. 1.0 Si1000/1/2/3/4/5 109 ...
Page 110
... Si1000/1/2/3/4/5 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time. Clocks to Execute 1 Number of Instructions 26 8.2. Programming and Debugging Support In-system programming of the Flash program memory and communication with on-chip debug support logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2) ...
Page 111
... direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte Si1000/1/2/3/4/5 Description Rev. 1.0 Bytes Clock Cycles ...
Page 112
... Si1000/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A Rotate A right through Carry SWAP A Swap nibbles of A Data Transfer ...
Page 113
... Compare immediate to Register and jump if not equal CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation Si1000/1/2/3/4/5 Description Rev. 1.0 Bytes Clock Cycles ...
Page 114
... Si1000/1/2/3/4/5 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00– ...
Page 115
... Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x83 Bit Name 7:0 DPH[7:0] Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi- rectly addressed Flash memory or XRAM. Si1000/1/2/3/4 DPL[7:0] R Function DPH[7:0] R/W ...
Page 116
... Si1000/1/2/3/4/5 SFR Definition 8.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incre- mented before every PUSH operation. The SP register defaults to 0x07 after reset. ...
Page 117
... This is a bit-addressable, general purpose flag for use under software control. 0 PARITY Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even RS[1:0] R/W R Function Rev. 1.0 Si1000/1/2/3/4 PARITY R/W R 117 ...
Page 118
... The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The memory organization of the Si1000/1/2/3/4/5 device family is shown in Figure 9 RAM / (FLA SH) ...
Page 119
... Data Memory The Si1000/1/2/3/4/5 device family includes 4352 bytes of RAM data memory. 256 bytes of this memory is mapped into the internal RAM space of the 8051. 4096 bytes of this memory is on-chip “external” memory. The data memory map is shown in Figure 9.1 for reference. ...
Page 120
... SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 9.1 illustrates the data memory organization of the Si1000/1/2/3/4/5. 9.2.1.1. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- eral-purpose registers ...
Page 121
... On-Chip XRAM The Si1000/1/2/3/4/5 MCUs include on-chip RAM mapped into the external data memory space (XRAM). The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in either the data pointer (DPTR), or with the target address low byte and the target address high byte in the External Memory Interface Control Register (EMI0CN, shown in SFR Defi- nition 10 ...
Page 122
... Si1000/1/2/3/4/5 10.2. Special Function Registers The special function register used for configuring XRAM access is EMI0CN. SFR Definition 10.1. EMI0CN: External Memory Interface Control Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xAA Bit Name 7:4 Unused Read = 0000b; Write = Don’t Care. ...
Page 123
... SFRs used to configure and access the sub-systems unique to the Si1000/1/2/3/4/5. This allows the addition of new functionality while retaining compatibility with the MCS- 51™ instruction set. Table 11.1 and Table 11.2 list the SFRs implemented in the Si1000/1/2/3/4/5 device family. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF ...
Page 124
... Si1000/1/2/3/4/5 11.1. SFR Paging To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been imple- mented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in Table 11.1. During device initialization, some SFRs located on SFR Page 0xF may need to be accessed. ...
Page 125
... CPT1MX 0x9E 0x0 CRC0AUTO 0x96 0xF CRC0CN 0x92 0xF CRC0CNT 0x97 0xF CRC0DAT 0x91 0xF CRC0FLIP 0x95 0xF Si1000/1/2/3/4 SFRPAGE[7:0] R Function Description Accumulator ADC0 Accumulator Configuration ADC0 Configuration ADC0 Control ADC0 Greater-Than Compare High ADC0 Greater-Than Compare Low ADC0 High ADC0 Low ...
Page 126
... Si1000/1/2/3/4/5 Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SFR Page CRC0IN 0x93 0xF DC0CF 0x96 0x0 DC0CN 0x97 0x0 DPH 0x83 All DPL 0x82 All EIE1 0xE6 All EIE2 ...
Page 127
... SPI1CKR 0x85 0x0 SPI1CN 0xB0 0x0 SPI1DAT 0x86 0x0 Si1000/1/2/3/4/5 Description PCA0 Capture 5 High PCA0 Capture 0 Low PCA0 Capture 1 Low PCA0 Capture 2 Low PCA0 Capture 3 Low PCA0 Capture 4 Low PCA0 Capture 5 Low PCA0 Module 0 Mode Register PCA0 Module 1 Mode Register ...
Page 128
... Si1000/1/2/3/4/5 Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SFR Page TCON 0x88 0x0 TH0 0x8C 0x0 TH1 0x8D 0x0 TL0 0x8A 0x0 TL1 0x8B 0x0 TMOD 0x89 0x0 TMR2CN ...
Page 129
... Interrupt Handler The Si1000/1/2/3/4/5 microcontroller family includes an extended interrupt system supporting multiple interrupt sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Refer to Table 12.1, “Interrupt Summary,” on page 131 for a detailed listing of all interrupt sources supported by the device. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s) ...
Page 130
... Si1000/1/2/3/4/5 12.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted high priority interrupt preempts a low priority interrupt, the low priority interrupt will finish execution after the high priority interrupt completes ...
Page 131
... ADC0 End of Conversion 0x0053 Programmable Counter 0x005B Array Comparator0 0x0063 Comparator1 0x006B Timer 3 Overflow 0x0073 VDD_MCU Supply 0x007B Monitor Early Warning Port Match 0x0083 Si1000/1/2/3/4/5 Pending Flag Top None N/A N/A Always 0 IE0 (TCON. TF0 (TCON. IE1 (TCON. TF1 (TCON.7) ...
Page 132
... Si1000/1/2/3/4/5 Table 12.1. Interrupt Summary (Continued) Interrupt Source SmaRTClock Oscillator 0x008B Fail EZRadioPRO Serial 0x0093 Interface (SPI1) Notes: 1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from vectoring to the associated interrupt service routine. 2. Indicates a register located in an indirect memory space. ...
Page 133
... Enable interrupt requests generated by the TF0 flag. 0 EX0 Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 input ET2 ES0 ET1 R/W R/W R Function Rev. 1.0 Si1000/1/2/3/4 EX1 ET0 EX0 R/W R/W R 133 ...
Page 134
... Si1000/1/2/3/4/5 SFR Definition 12.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Page = 0x0; SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Read = 1b, Write = don't care. 6 PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. ...
Page 135
... Enable interrupt requests generated by a SmaRTClock Alarm. 0 ESMB0 Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0 ECP0 EPCA0 EADC0 EWADC0 R/W R/W R Function Rev. 1.0 Si1000/1/2/3/4 ERTC0A ESMB0 R/W R/W R 135 ...
Page 136
... Si1000/1/2/3/4/5 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 PCP1 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. ...
Page 137
... EWARN Enable VDD_MCU Supply Monitor Early Warning Interrupt. This bit sets the masking of the VDD_MCU Supply Monitor Early Warning interrupt. 0: Disable the VDD_MCU Supply Monitor Early Warning interrupt. 1: Enable interrupt requests generated by VDD_MCU Supply Monitor ESPI1 ERTC0F R/W R/W R Function Rev. 1.0 Si1000/1/2/3/4 EMAT EWARN R/W R/W R 137 ...
Page 138
... Si1000/1/2/3/4/5 SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name R R Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xF7 Bit Name 7:4 Unused Read = 0000b. Write = Don’t care. PSPI1 3 Serial Peripheral Interface (SPI1) Interrupt Priority Control. This bit sets the priority of the SPI1 interrupt. ...
Page 139
... IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. Si1000/1/2/3/4/5 IT1 IN1PL INT1 Interrupt ...
Page 140
... Si1000/1/2/3/4/5 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input is active high. 6:4 IN1SL[2:0] INT1 Port Pin Selection Bits. ...
Page 141
... The Flash lock resets after each write or erase; the key codes must be written again before a following Flash operation can be per- formed. The FLKEY register is detailed in SFR Definition 13.2. Si1000/1/2/3/4/5 Monitor and enabling the V DD ...
Page 142
... Si1000/1/2/3/4/5 13.1.2. Flash Erase Procedure The Flash memory is organized in 1024-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire 1024-byte page, perform the following steps: 1. Save current interrupt state and disable interrupts. 2. Set the PSEE bit (register PSCTL). ...
Page 143
... Flash Security Lock Byte is unlocked when no other Flash pages are locked (all bits of the Lock Byte are 1) and locked when any other Flash pages are locked (any bit of the Lock Byte is 0). See the Si1000 example below. Security Lock Byte: ...
Page 144
... The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Table 13.1 summarizes the Flash security features of the Si1000/1/2/3/4/5 devices. Table 13.1. Flash Security Summary Action ...
Page 145
... Monitor and enabling the found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website. Notes: On Si1000/1/2/3/4/5 devices, both the V or erase Flash without generating a Flash Error Device Reset. On Si1000/1/2/3/4/5 devices, both the V after a power-on reset. ...
Page 146
... Si1000/1/2/3/4/5 5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect. 6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit Areas to check are initialization code which enables other reset sources, such as the Missing Clock Detector or Comparator, for example, and instructions which force a Software Reset. A global search on " ...
Page 147
... Flash read current depends on the number of address lines that toggle between sequential Flash read operations. In most cases, the difference in power is relatively small (on the order of 5%). 4. The Flash memory is organized in rows. Each row in the Si1000/1/2/3/4/5 Flash contains 128 bytes. A substantial current increase can be detected when the read address jumps from one row in the Flash memory to another. Consider a 3-cycle loop (e.g., SJMP $, or while(1) ...
Page 148
... Si1000/1/2/3/4/5 SFR Definition 13.1. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Page =0x0; SFR Address = 0x8F Bit Name 7:3 Unused Read = 00000b, Write = don’t care. 2 SFLE Scratchpad Flash Memory Access Enable. When this bit is set, Flash MOVC reads and MOVX writes from user software are directed to the Scratchpad Flash sector ...
Page 149
... Flash, it can intentionally lock the Flash by writing a non-0xA5 value to FLKEY from software. Read: When read, bits 1–0 indicate the current Flash lock state. 00: Flash is write/erase locked. 01: The first key code has been written (0xA5). 10: Flash is unlocked (writes/erases allowed). 11: Flash writes/erases disabled until the next reset. Si1000/1/2/3/4 FLKEY[7:0] R ...
Page 150
... Si1000/1/2/3/4/5 SFR Definition 13.3. FLSCL: Flash Scale Bit 7 6 BYPASS Name R R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB6 Bit Name 7 Reserved Always Write BYPASS Flash Read Timing One-Shot Bypass. 0: The one-shot determines the Flash read time. This setting should be used for oper- ating frequencies less than 10 MHz ...
Page 151
... Power Management Si1000/1/2/3/4/5 devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The power management unit (PMU0) allows the device to enter and wake-up from the available power modes. A brief description of each power mode is provided in Table 14.1. Detailed descriptions of each mode can be found in the following sections ...
Page 152
... One-cell: 0.9 to 1.8 V VBAT Two-cell: 1.8 to 3.6 V 1.9 V typical DC0 One-Cell Active/ Idle/Stop/Suspend One-Cell Sleep Sleep PMU0 SmaRTClock Figure 14.1. Si1000/1/2/3/4/5 Power Distribution 152 VDD/DC+ One-cell or Two-cell: 1.8 to 3.6 V Note: VDD/DC+ must be > VBAT Analog Peripherals VREF A 10-bit M 300 ksps U ADC ...
Page 153
... Stop Mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep or Suspend mode will provide more power savings if the MCU needs to be inactive for a long period of time. On Si1000/1/2/3/4/5 devices, the Precision Oscillator Bias is not automatically disabled and should be dis- abled by software to achieve the lowest possible Stop mode current. ...
Page 154
... Si1000/1/2/3/4/5 14.4. Suspend Mode Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal oscillators disabled. All digital logic (timers, communication peripherals, interrupts, CPU, etc.) stops functioning until one of the enabled wake-up sources occurs. ...
Page 155
... RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT (or VDD_MCU on Si1000/1/2/3 devices) does not fall below V information is preserved allowing the device to resume code execution upon waking up from sleep mode. The following wake-up sources can be configured to wake the device from sleep mode: SmaRTClock Oscillator Fail ...
Page 156
... Si1000/1/2/3/4/5 SFR Definition 14.1. PMU0CF: Power Management Unit Configuration Bit 7 6 SLEEP SUSPEND CLEAR Name W W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB5 Bit Name Description 7 SLEEP Sleep Mode Select 6 SUSPEND Suspend Mode Select 5 CLEAR Wake-up Flag Clear 4 RSTWK ...
Page 157
... Name Description 7:2 GF[5:0] General Purpose Flags 1 STOP Stop Mode Select 0 IDLE Idle Mode Select 14.8. Power Management Specifications See Table 4.5 on page 58 for detailed Power Management Specifications. Si1000/1/2/3/4 GF[5:0] R Write Sets the logic value. Writing 1 places the device in Stop Mode. ...
Page 158
... Si1000/1/2/3/4/5 15. Cyclic Redundancy Check Unit (CRC0) Si1000/1/2/3/4/5 devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed indi- rectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 15 ...
Page 159
... CRC value CRC_acc = CRC_acc << Return the final remainder (CRC value) return CRC_acc; } The following table lists several input values and the associated outputs using the 16-bit Si1000/1/2/3/4/5 CRC algorithm: Table 15.1. Example 16-bit CRC Outputs Input 0x63 0x8C 0x7D ...
Page 160
... Si1000/1/2/3/4/5 15.2. Preparing for a CRC Calculation To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0 result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF. The following steps can be used to initialize CRC0 ...
Page 161
... An example of such an instruction is a 3-byte MOV that targets the CRC0FLIP register. When programming in ‘C’, the dummy value written to CRC0FLIP should be a non-zero value to prevent the compiler from generating a 2-byte MOV instruction CRC0SEL CRC0INIT CRC0VAL R/W R/W R Function Rev. 1.0 Si1000/1/2/3/4 CRC0PNT[1:0] R/W R 161 ...
Page 162
... Si1000/1/2/3/4/5 SFR Definition 15.2. CRC0IN: CRC0 Data Input Bit 7 6 Name Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x93 Bit Name 7:0 CRC0IN[7:0] CRC0 Data Input. Each write to CRC0IN results in the written data being computed into the existing CRC result according to the CRC algorithm described in Section 15.1 SFR Definition 15 ...
Page 163
... Read = 00b; Write = Don’t Care. 5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count. These bits specify the number of Flash sectors to include in an automatic CRC calculation. The starting address of the last Flash sector included in the automatic CRC calculation is (CRC0ST+CRC0CNT) x 1024. Si1000/1/2/3/4 CRC0ST[5:0] ...
Page 164
... Si1000/1/2/3/4/5 15.5. CRC0 Bit Reverse Feature CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 15.2. Each byte of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLIP, the data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FFT. ...
Page 165
... Diode Bypass switch resistance, peak inductor current, and minimum duty cycle. VBAT 0.68 uH DCEN 4.7 uF Duty Cycle Control L parasitic GND/VBAT- Figure 16.1. DC-DC Converter Block Diagram Si1000/1/2/3/4/5 DC/DC Converter Diode Bypass Control Logic Voltage DC0CN Reference DC/DC DC0CF Oscillator L parasitic Rev ...
Page 166
... Si1000/1/2/3/4/5 16.1. Startup Behavior On initial power-on, the dc-dc converter outputs a constant 50% duty cycle until there is sufficient voltage on the output capacitor to maintain regulation. The size of the output capacitor and the amount of load cur- rent present during startup will determine the length of time it takes to charge the output capacitor. ...
Page 167
... Note that the device can only switch between one-cell and two-cell mode during a power-on reset. See Section “18. Reset Sources” on page 175 for more information regarding reset behavior. Figure 16.2 shows the two dc-dc converter configuration options. Si1000/1/2/3/4/5 Supply Monitor resets if there DD Rev. 1.0 ...
Page 168
... Si1000/1/2/3/4/5 DC-DC Converter Enabled 0.9 to 1.8 V Supply Voltage (one-cell mode) DC-DC Converter Disabled 1.8 to 3.6 V Supply Voltage (two-cell mode) Figure 16.2. DC-DC Converter Configuration Options When the dc-dc converter “Enabled” configuration (one-cell mode) is chosen, the following guidelines apply: In most cases, the GND/VBAT– ...
Page 169
... These options can be used to minimize interference in noise sensitive applications. 16.8. DC-DC Converter Behavior in Sleep Mode When the Si1000/1/2/3/4/5 devices are placed in Sleep mode, the dc-dc converter is disabled, and the VDD_MCU/DC+ output is internally connected to VBAT by default. This behavior ensures that the GPIO pins are powered from a low-impedance source during sleep mode ...
Page 170
... Si1000/1/2/3/4/5 from VBAT to ground when the VDD_MCU/DC+ level falls below VBAT, but this leakage current should be small compared to the current from VDD_MCU/DC+. The amount of time that it takes for a device configured in one-cell mode to wake up from Sleep mode depends on a number of factors, including the dc-dc converter clock speed, the settings of the SWSEL and ILIMIT bits, the battery internal resistance, the load current, and the difference between the VBAT voltage level and the programmed output voltage. The wake up time can be as short as 2 µ ...
Page 171
... Target output voltage is 1.9 V. 010: Target output voltage is 2.0 V. 011: Target output voltage is 2.1 V. 100: Target output voltage is 2.4 V. 101: Target output voltage is 2.7 V. 110: Target output voltage is 3.0 V. 111: Target output voltage is 3 Reserved SYNC R/W R/W R Function Rev. 1.0 Si1000/1/2/3/4 VSEL R 171 ...
Page 172
... Si1000/1/2/3/4/5 SFR Definition 16.2. DC0CF: DC-DC Converter Configuration Bit 7 6 Name Reserved CLKDIV[1:0] R R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0x96 Bit Name 7 Reserved Read = 0b; Must write 0b. 6:5 CLKDIV[1: Clock Divider. Divides the dc-dc converter clock when the system clock is selected as the clock source for dc-dc converter ...
Page 173
... DC-DC Converter Specifications See Table 4.14 on page 65 for a detailed listing of dc-dc converter specifications. Si1000/1/2/3/4/5 Rev. 1.0 173 ...
Page 174
... Si1000/1/2/3/4/5 17. Voltage Regulator (VREG0) Si1000/1/2/3/4/5 devices include an internal voltage regulator (VREG0) to regulate the internal core supply to 1.8 V from a VDD_MCU supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are specified in the Electrical Specifications chapter. The REG0CN register allows the Precision Oscillator Bias to be disabled, saving approximately 80 µA in all non-Sleep power modes ...
Page 175
... Power On Reset Supply (wired-OR) Monitor + 0 - Enable PCA (Software Reset) WDT SWRSF EN Illegal Flash System Reset Power Management Block (PMU0) Reset Figure 18.1. Reset Sources Rev. 1.0 *On Si1000/1/2/3 devices, VBAT is internally connected to VDD_MCU. RST Reset Funnel Operation System Reset Power-On Reset 175 ...
Page 176
... Since all resets cause program execution to begin at the same location (0x0000), software can read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data memory should be assumed to be undefined after a power-on reset. Note: Si1000/1/2/3 have the VBAT signal internally connected to VDD_MCU. ~0.8 V ...
Page 177
... Power-Fail (VDD_MCU Supply Monitor) Reset Si1000/1/2/3/4/5 devices have a VDD_MCU Supply Monitor that is enabled and selected as a reset source after each power-on or power-fail reset. When enabled and selected as a reset source, any power down transition or power irregularity that causes VDD_MCU to drop below V driven low and the CIP-51 will be held in a reset state (see Figure 18 ...
Page 178
... Si1000/1/2/3/4/5 Important Notes: The Power-on Reset (POR) delay is not incurred after a VDD_MCU supply monitor reset. See Section “4. Electrical Characteristics” on page 40 for complete electrical characteristics of the VDD_MCU monitor. Software should take care not to inadvertently disable the V to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should explicitly set PORSF to '1' to keep the V The VDD_MCU supply monitor must be enabled before selecting reset source ...
Page 179
... The missing clock detector reset is automatically disabled when the device is in the low power Suspend or Sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset source is restored to its previous value. The state of the RST pin is unaffected by this reset. Si1000/1/2/3/4 ...
Page 180
... Si1000/1/2/3/4/5 18.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non- inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the reset source ...
Page 181
... Enable the MCD. The MCD triggers a reset if a missing clock condition is detected. 0: Disable the VDD_MCU Supply Monitor as a reset source. 1: Enable the VDD_MCU Supply Monitor as a reset 3 source. N/A Rev. 1.0 Si1000/1/2/3/4 PORSF PINRSF R/W R/W R Varies Varies Varies Read Set SmaRTClock alarm or oscillator fail caused the last reset ...
Page 182
... Si1000/1/2/3/4/5 19. Clocking Sources Si1000/1/2/3/4/5 devices include a programmable precision internal oscillator, an external oscillator drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 19.1. The external oscillator can be configured using the OSCXCN register. The low power internal oscillator is automatically enabled and disabled when selected and deselected as a clock source ...
Page 183
... MHz to 24.3 MHz. 19.2. Low Power Internal Oscillator All Si1000/1/2/3/4/5 devices include a low power internal oscillator that defaults as the system clock after a system reset. The low power internal oscillator frequency is 20 MHz ± 10% and is automatically enabled when selected as the system clock and disabled when not in use. See Section “ ...
Page 184
... Si1000/1/2/3/4 MHz 15 pF Figure 19.2. 25 MHz External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference ...
Page 185
... When the RC oscillator is first enabled, the external oscillator valid detector allows software to determine when oscillation has stabilized. The recommended procedure for starting the RC oscillator is: 1. Configure XTAL2 for analog I/O and disable the digital output drivers. 2. Configure and enable the external oscillator. Si1000/1/2/3/4/5 K Factor (C Mode) Typical Supply Current/ Actual Measured Frequency (C Mode, VDD = 2 ...
Page 186
... Si1000/1/2/3/4/5 3. Poll for XTLVLD > Switch the system clock to the external oscillator. 19.3.3. External Capacitor Mode If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 19.1, Option 3. The capacitor should be added to XTAL2, and XTAL2 should be configured for analog I/O with the digital output drivers disabled. XTAL1 is not affected in RC mode. The capacitor should be no greater than 100 pF ...
Page 187
... Special Function Registers for Selecting and Configuring the System Clock The clocking sources on Si1000/1/2/3/4/5 devices are enabled and configured using the OSCICN, OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time Clock)” on page 190 for SmaRTClock register descriptions. The system clock source for the MCU can be selected using the CLKSEL register ...
Page 188
... Si1000/1/2/3/4/5 SFR Definition 19.2. OSCICN: Internal Oscillator Control Bit 7 6 IOSCEN IFRDY Name R/W R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB2 Bit Name 7 IOSCEN Internal Oscillator Enable. 0: Internal oscillator disabled. 1: Internal oscillator enabled. IFRDY 6 Internal Oscillator Frequency Ready Flag . ...
Page 189
... Reserved Read = 0b. Must Write 0b. 2:0 XFCN External Oscillator Frequency Control Bits. Controls the external oscillator bias current. 000-111: See Table 19.1 on page 184 (Crystal Mode) or Table 19.2 on page 185 ( Mode) for recommended settings Reserved R/W R/W R Function Rev. 1.0 Si1000/1/2/3/4 XFCN[2:0] R/W R/W R 189 ...
Page 190
... Si1000/1/2/3/4/5 20. SmaRTClock (Real Time Clock) Si1000/1/2/3/4/5 devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with alarm. The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a crystal. No external resistor or loading capacitors are required. The on-chip loading capacitors are pro- grammable to 16 discrete levels allowing compatibility with a wide range of crystals. The SmaRTClock can operate directly from a 0.9– ...
Page 191
... RTC0PIN SmaRTClock Pin Configuration Register 0x08–0x0B ALARMn SmaRTClock Alarm Registers Si1000/1/2/3/4/5 Description Four Registers used for setting the 32-bit SmaRTClock timer or reading its current value. Controls the operation of the SmaRTClock State Machine. Controls the operation of the SmaRTClock Oscillator. Controls the value of the progammable oscillator load capacitance and enables/disables AutoStep ...
Page 192
... Si1000/1/2/3/4/5 20.1.1. SmaRTClock Lock and Key Functions The SmaRTClock Interface is protected with a lock and key function. The SmaRTClock Lock and Key Reg- ister (RTC0KEY) must be written with the correct key codes, in sequence, before writes and reads to RTC0ADR and RTC0DAT may be performed. The key codes are: 0xA5, 0xF1. There are no timing restric- tions, but the key codes must be written in order ...
Page 193
... A, RTC0DAT nop nop mov A, RTC0DAT Recommended Instruction Timing for a multi-byte register write with short strobe enabled: mov RTC0ADR, #010h mov RTC0DAT, #05h nop mov RTC0DAT, #06h nop mov RTC0DAT, #07h nop mov RTC0DAT, #08h nop Si1000/1/2/3/4/5 Rev. 1.0 193 ...
Page 194
... Si1000/1/2/3/4/5 SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xAE Bit Name 7:0 RTC0ST SmaRTClock Interface Lock/Key and Status. Locks/unlocks the SmaRTClock interface when written. Provides lock status when read. ...
Page 195
... ADDR[3:0] SmaRTClock Indirect Register Address. Sets the currently selected SmaRTClock register. See Table 20.1 for a listing of all SmaRTClock indirect registers. Note: The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMn internal SmaRTClock register. Si1000/1/2/3/4 SHORT R R/W ...
Page 196
... Si1000/1/2/3/4/5 SFR Definition 20.3. RTC0DAT: SmaRTClock Data Bit 7 6 Name Type 0 0 Reset SFR Page= 0x0; SFR Address = 0xAD Bit Name 7:0 RTC0DAT SmaRTClock Data Bits. Holds data transferred to/from the internal SmaRTClock register selected by RTC0ADR. Note: Read-modify-write instructions (orl, anl, etc.) should not be used on this register. ...
Page 197
... Set SmaRTClock to Self-Oscillate Mode (XMODE = 0). 2. Set the desired oscillation frequency: For oscillation at about 20 kHz, set BIASX2 = 0. For oscillation at about 40 kHz, set BIASX2 = 1. 3. The oscillator starts oscillating instantaneously. 4. Fine tune the oscillation frequency by adjusting the load capacitance (RTC0XCF). Si1000/1/2/3/4/5 Rev. 1.0 197 ...
Page 198
... Si1000/1/2/3/4/5 20.2.3. Programmable Load Capacitance The programmable load capacitance has 16 values to support crystal oscillators with a wide range of rec- ommended load capacitance. If Automatic Load Capacitance Stepping is enabled, the crystal load capaci- tors start at the smallest setting to allow a fast startup time, then slowly increase the capacitance until the final programmed value is reached ...
Page 199
... High crystal drive strength is recommended when the crystal is exposed to poor environmen- tal conditions such as excessive moisture. SmaRTClock Bias Doubling is enabled by setting BIASX2 (RTC0XCN. Si1000/1/2/3/4/5 Low Risk of Clock High Risk of Clock Failure ...
Page 200
... Si1000/1/2/3/4/5 . Table 20.3. SmaRTClock Bias Settings Mode Crystal Self-Oscillate 20.2.5. Missing SmaRTClock Detector The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN. When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if SmaRTClock oscillator remains high or low for more than 100 µs. ...