ATMEGA64RZAV-10MU Atmel, ATMEGA64RZAV-10MU Datasheet - Page 75

• Manufacturer Part Number: ATMEGA64RZAV-10MU
• Description: MCU ATMEGA644/AT86RF230 44-QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-VFQFN Exposed Pad
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

10 Radio Transceiver Usage
10.1 Frame Receive Procedure
10.2 Frame Transmit Procedure
5131E-MCU Wireless-02/09
This section describes basic procedures to receive and transmit frames using the
AT86RF230. For a detailed programming description refer to application note AVR2009
“AT86RF230 – Software Programming Model”.
While in state RX_ON the radio transceiver searches for incoming frames on the
selected channel. A detection of a valid IEEE 802.15.4 frame is indicated by an IRQ_2
(RX_START) interrupt. The frame reception is completed when issuing the IRQ_3
(TRX_END) interrupt. Waiting for IRQ_3 (TRX_END) interrupt before uploading the
frame to the microcontroller is recommended for operations considered to be non time
critical. Figure 9-6 illustrates the frame receive procedure.
Figure 9-6. Frame Receive Procedure - Transactions between AT86RF230 and
Microcontroller
Critical protocol timing could require starting the frame upload as soon as possible. The
first byte of the frame data can be read 32 µs after the IRQ_2 (RX_START) interrupt.
The microcontroller must ensure to read slower than the frame is received. Otherwise,
the Frame Buffer wills under run, IRQ_6 (TRX_UR) interrupt is issued. The frame data
are not valid anymore and need to read again. The LQI byte can be uploaded to the
microcontroller after the IRQ_3 (TRX_END) interrupt was issued.
A frame transmission comprises two actions, a frame download to the Frame Buffer and
the transmission of the Frame Buffer content. Both actions can be run in parallel if
required by critical protocol timing.
Figure 9-7 illustrates the frame transmit procedure, when downloading and transmitting
the frame consecutively. After a frame download by a Frame Buffer write access, the
frame transmission is initiated by asserting pin SLP_TR or writing the TRX command
TX_START to register 0x02 (TRX_STATE), while the radio transceiver is in state
PLL_ON. The completion of the transmission is indicated by an IRQ_3 (TRX_END)
interrupt.
AT86RF230
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