ATMEGA64RZAV-10MU Atmel, ATMEGA64RZAV-10MU Datasheet - Page 25

• Manufacturer Part Number: ATMEGA64RZAV-10MU
• Description: MCU ATMEGA644/AT86RF230 44-QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-VFQFN Exposed Pad
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

Figure 7-2. Timing of RX_START and TRX_END Interrupts in Basic Operating Mode (see register 0x0F)
7.1.4 Basic Mode Timing
7.1.4.1 Power-on and Wake-up Procedure
Figure 7-3. Wake-Up Procedure from SLEEP and P_ON to RX_ON (PLL Locked)
Signals/Events
State
Active Blocks
Command
Pin
Signals/Events
State
Active Blocks
Command
5131E-MCU Wireless-02/09
Typ. Processing Delay
Typ. Processing Delay
Number of Octets
Frame Content
TRX_STATE
TRX_STATE
SLEEP
SLP_TR
IRQ
IRQ
0
P_ON
EVDD on
SLP_TR=0
XOSC
XOSC
PLL_ON
~400
-16
XOSC delivers
clock
Timer 128 s
Timer 128 s
CLKM_CTRL
0
The following paragraphs depict the transitions between states and their timing.
The power-on sequence and the wake-up procedure is shown in Figure 7-3.
Setting pin SLP_TR = L in SLEEP state enables the crystal oscillator. After 0.4 ms
(typ.), the internal clock signal is available. After another 128 µs the clock signal is
provided at the CLKM pin if enabled. An additional 256 µs timer ensures that frequency
stability is sufficient to drive filter tuning (FTN) and the PLL. After the digital voltage
regulator has been settled, the radio transceiver enters the TRX_OFF state and waits
for further commands.
16 µs
μ
RX_LISTEN
μ
500
Preamble
CLKM delivers
clock
TRX_OFF
4
Timer 256 s
600
128
μ
SFD
1
BUSY_TX
160
700
PHR
1
RX_START
192
8 µs
Clock
stable
FTN BG
800
BUSY_RX
DVREG
PLL_ON,
RX_ON
PSDU
5
900
TRX_OFF
AVREG
Typical block settling time, stays on
Block active
waiting for SPI commands
352
16
μ
1000
s
AT86RF230
PLL_ON
RX_ON
TRX_END
PLL_ON
RX_LISTEN
16 µs
PLL
TRX_END
time [µs]
RX_ON
1100
IRQ
PLL locked
Time [μs]
Time [μs]
25