ATMEGA64RZAV-10MU Atmel, ATMEGA64RZAV-10MU Datasheet - Page 72

• Manufacturer Part Number: ATMEGA64RZAV-10MU
• Description: MCU ATMEGA644/AT86RF230 44-QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-VFQFN Exposed Pad
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

9.7.4 PLL Interrupt Handling
9.7.5 Register Description
72
AT86RF230
Bit
0x08
Read/Write
Reset value
Bit
0x08
Read/Write
Reset value
(PLL_DCU). To start the calibrations routines the device should be in state PLL_ON.
The center frequency tuning takes a maximum of 80 µs. The completion is indicated by
a PLL_LOCK interrupt. The delay cell calibration loop is completed after 6 µs. This is
typically not indicated by a PLL_LOCK interrupt.
There are two different interrupts indicating the PLL status (see register 0x0F). The
PLL_LOCK interrupt indicates that the PLL has locked. The PLL_UNLOCK interrupt
indicates an unexpected unlock condition. A PLL_LOCK interrupt clears any preceding
PLL_UNLOCK interrupt automatically and vice versa.
A PLL_LOCK interrupt occurs in the following situations:
• State change from TRX_OFF to PLL_ON/RX_ON
• Channel change in states PLL_ON/RX_ON
• Initiating a center frequency tuning manually
The state transition from BUSY_TX to PLL_ON can also initiate a PLL_LOCK interrupt,
due to the PLL settling back to the RX frequency.
Any other occurrences of PLL interrupts indicate erroneous behavior and require
checking of the actual device status.
Register 0x08 (PHY_CC_CCA)
The PHY_CC_CCA register contains register bits to initiate and control the CCA
measurement as well as to set the channel center frequency.
• Bit 7 – CCA_REQUEST
Refer to section 8.6.4.
• Bit [6:5] – CCA_MODE
Refer to section 8.6.4.
• Bit [4:0] – CHANNEL
The register bits CHANNEL define the RX/TX channel. The channel assignment is
according to IEEE 802.15.4.
Table 9-14. Channel Assignment for IEEE 802.15.4 – 2.4 GHz Band
Register Bit
CHANNEL
CCA_REQUEST
R/W
R/W
7
0
3
1
Value
0x0B
0x0C
0x0D
0x0E
R/W
R/W
6
0
2
0
CCA_MODE
CHANNEL
Channel Number
12
13
14
11
R/W
R/W
5
1
1
1
CHANNEL
Center Frequency [MHz]
R/W
R/W
4
0
0
1
5131E-MCU Wireless-02/09
2410
2415
2420
2405
PHY_CC_CCA
PHY_CC_CCA