ATMEGA64RZAV-10MU Atmel, ATMEGA64RZAV-10MU Datasheet - Page 14

• Manufacturer Part Number: ATMEGA64RZAV-10MU
• Description: MCU ATMEGA644/AT86RF230 44-QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-VFQFN Exposed Pad
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

Figure 6-8. Packet Structure - Frame Buffer Read Access
Figure 6-9. Example SPI Sequence - Frame Buffer Write Sequence of a Frame with 4-byte PSDU
Figure 6-10. Example SPI Sequence - Frame Buffer Read Sequence of a Frame with 4-byte PSDU
6.2.3 SRAM Access Mode
SCLK
MOSI
MISO
SCLK
MOSI
MISO
14
SEL
SEL
AT86RF230
COMMAND
COMMAND
XX
XX
PHR
The number of bytes n for one Frame Buffer access is calculated as follow:
Receive:
Transmit:
The maximum value of frame_length is 127 bytes. That means that n ≤ 130 for Frame
Buffer read access and n ≤ 129 for Frame Buffer write access. Each read or write of a
data byte increments automatically the address counter of the Frame Buffer until the
access is terminated by setting SEL = H.
Figure 6-9 and Figure 6-10 illustrate an example SPI sequence of a Frame Buffer
access to write and read a frame with 4-byte PSDU respectively.
XX
Access violations during a Frame Buffer write or read access are indicated by a
TRX_UR interrupt. For further details refer to section 9.3.3.
The SRAM access mode allows access to certain bytes within the Frame Buffer. This
may reduce SPI traffic.
PHR
XX
PSDU 1
PSDU 1
XX
XX
n = 3 + frame_length
[command byte, frame length byte, PSDU data, LQI byte]
n = 2 + frame_length
[command byte, frame length byte, PSDU data]
PSDU 2
PSDU 2
XX
XX
PSDU 3
PSDU 3
XX
XX
PSDU 4
PSDU 4
XX
XX
5131E-MCU Wireless-02/09
LQI
XX