ATMEGA64RZAV-10MU Atmel, ATMEGA64RZAV-10MU Datasheet - Page 49

• Manufacturer Part Number: ATMEGA64RZAV-10MU
• Description: MCU ATMEGA644/AT86RF230 44-QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-VFQFN Exposed Pad
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

8.2.3 Automatic FCS generation
8.2.4 Automatic FCS check
8.2.5 Register Description
5131E-MCU Wireless-02/09
Bit
0x05
Read/Write
Reset value
Bit
0x05
Read/Write
Reset value
The AT86RF230 automatic FCS generation and insertion is enabled by setting register
bit TX_AUTO_CRC_ON to 1.
For a frame with a frame length field (PHR) specified as N (3 ≤ N ≤ 127), the FCS is
calculated on the first N -2 PSDU octets in the Frame Buffer, and the resulting 16 bit
FCS field is appended during transmission. Note, if the AT86RF230 automatic FCS
generation is enabled, the frame download to the Frame Buffer can be stopped right
after MAC payload. There is no need to download FCS dummy bytes.
In RX_AACK states, when a received frame needs to be acknowledged, the FCS of the
ACK frame is always automatically generated by the AT86RF230.
Example:
A frame transmission of length five with the register bit TX_AUTO_CRC_ON set, is
started with a frame download of five bytes (the last two bytes can be omitted). The first
three bytes are used for FCS generation, the last two bytes are replaced by the
internally calculated FCS.
An FCS check is applied on each incoming frame with a frame length N ≥ 2. The result
of the FCS check is stored to register bit RX_CRC_VALID in register 0x06
(PHY_RSSI). The register bit is updated at the event of the TRX_END interrupt and
remains valid until the next TRX_END interrupt caused by a new frame reception.
In RX_AACK states, if FCS of the received frame is not valid, the radio transceiver
rejects the frame and the TRX_END interrupt will not be generated.
In TX_ARET states, the FCS of an ACK is automatically checked. If it is not correct, the
ACK is not accepted.
Register 0x05 (PHY_TX_PWR)
The PHY_TX_PWR register sets the transmit power and controls the FCS algorithm for
TX operation.
• Bit 7 – TX_AUTO_CRC_ON
Register bit TX_AUTO_CRC_ON controls the automatic FCS generation for TX
operation. The automatic FCS algorithm is performed autonomously by the radio
transceiver if register bit TX_AUTO_CRC_ON = 1.
• Bit [6:4] – Reserved
• Bit [3:0] – TX_PWR
Refer to section 9.2.3.
TX_AUTO_CRC_ON
R/W
R/W
3
0
7
0
R/W
2
0
R
6
0
TX_PWR
Reserved
R/W
1
0
R
5
0
R/W
AT86RF230
0
0
R
4
0
PHY_TX_PWR
PHY_TX_PWR
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