MCIMX31LVKN5 Freescale Semiconductor, MCIMX31LVKN5 Datasheet - Page 71

• Manufacturer Part Number: MCIMX31LVKN5
• Description: IC MPU MAP I.MX31L 457-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX31r

Specifications of MCIMX31LVKN5

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, POR, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.22 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 457-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Display read operation can be performed with wait states when each read access takes up to four display
interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the
DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers.
Figure 56
Freescale Semiconductor
DISPB_PAR_RS
DISPB_PAR_RS
DISPB_PAR_RS
DISPB_D#_CS
DISPB_WR
(READ/WRITE)
DISPB_D#_CS
DISPB_D#_CS
DISPB_WR
(READ/WRITE)
DISPB_WR
(READ/WRITE)
DISPB_BCLK
DISPB_DATA
DISPB_DATA
DISPB_DATA
DISPB_RD
(ENABLE)
DISPB_RD
(ENABLE)
DISPB_RD
(ENABLE)
Figure 55. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram
shows timing of the parallel interface with read wait states.
Single access mode (all control signals are not active for one display interface clock after each display access)
Burst access mode with sampling by separate burst clock (BCLK)
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Burst access mode with sampling by ENABLE signal
Electrical Characteristics
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