MCIMX31LVKN5 Freescale Semiconductor, MCIMX31LVKN5 Datasheet - Page 62

• Manufacturer Part Number: MCIMX31LVKN5
• Description: IC MPU MAP I.MX31L 457-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX31r

Specifications of MCIMX31LVKN5

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, POR, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.22 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 457-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Electrical Characteristics
Table 47
1
Display interface clock period average value.
62
Display interface clock period immediate value.
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_DRDY
IP10
IP11
IP12
IP13
IP14
IP15
IP5
IP6
IP7
IP8
IP9
ID
Tdicp
shows timing parameters of signals presented in
=
Display interface clock period
Display pixel clock period
Screen width
HSYNC width
Horizontal blank interval 1
Horizontal blank interval 2
HSYNC delay
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
⎧
⎪
⎪
⎨
⎪
⎪
⎩
IP11
T HSP_CLK
Table 47. Synchronous Display Interface Timing Parameters—Pixel Level
T HSP_CLK
Figure 48. TFT Panels Timing Diagram—Vertical Sync Pulse
Parameter
⋅
⎛
⎝
floor
⋅
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
IP13
HSP_CLK_PERIOD
Tdicp
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
HSP_CLK_PERIOD
=
T HSP_CLK
IP14
Symbol
Tdpcp
Thbi1
Thbi2
Tdicp
Thsw
Tvbi1
Tvbi2
Thsd
Tvsw
Tsw
⋅
Tsh
,
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
+
0.5 0.5
Figure 47
±
Tdicp
(DISP3_IF_CLK_CNT_D+1) * Tdicp
(SCREEN_WIDTH+1) * Tdpcp
(H_SYNC_WIDTH+1) * Tdpcp
BGXP * Tdpcp
(SCREEN_WIDTH – BGXP – FW) * Tdpcp
H_SYNC_DELAY * Tdpcp
(SCREEN_HEIGHT+1) * Tsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH+1) * Tdpcp
else
(V_SYNC_WIDTH+1) * Tsw
BGYP * Tsw
(SCREEN_HEIGHT – BGYP – FH) * Tsw
⎞
⎠
Start of frame
1
,
IP12
for integer
for fractional
and
Figure
Value
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
48.
HSP_CLK_PERIOD
End of frame
Freescale Semiconductor
IP15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns