MCIMX31LVKN5 Freescale Semiconductor, MCIMX31LVKN5 Datasheet - Page 61

• Manufacturer Part Number: MCIMX31LVKN5
• Description: IC MPU MAP I.MX31L 457-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX31r

Specifications of MCIMX31LVKN5

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, POR, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.22 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 457-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.3.15.2.2
Figure 47
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.
Figure 48
programmable.
Freescale Semiconductor
DISPB_D3_HSYNC
•
DISPB_D3_DRDY
DISPB_D3_DATA
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_HSYNC
DISPB_D3_DATA
DISPB_D3_CLK
DISPB_D3_DRDY
DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted onto the display. When disabled, the data is invalid and the trace is off.
DISPB_D3_CLK
Start of line
depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
depicts the vertical timing (timing of one frame). All figure parameters shown are
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 46. Interface Timing Diagram for TFT (Active Matrix) Panels
Figure 47. TFT Panels Timing Diagram—Horizontal Sync Pulse
LINE 1
IP5
1
IP8
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
LINE 2
2
IP9
LINE 3
3
LINE 4
IP7
IP6
LINE n-1
m-1
Electrical Characteristics
LINE n
IP10
m
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