MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 574
MCF5282CVF80
Manufacturer Part Number
MCF5282CVF80
Description
IC MPU 32BIT 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Controller Family/series
ColdFire
Ram Memory Size
64KB
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of Pwm Channels
8
Digital Ic Case Style
MAPBGA
Rohs Compliant
No
Package
256MA-BGA
Device Core
ColdFire
Family Name
MCF528x
Maximum Speed
80 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
150
Interface Type
CAN/Ethernet/I2C/QSPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
12
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Queued Analog-to-Digital Converter (QADC)
Trigger events which occur during the execution of a subqueue are ignored, but the trigger overrun flag is
set. When a continuous-scan mode is selected, a trigger event occurring after the completion of the last
subqueue (after the queue completion flag is set), causes the execution to continue with the first subqueue,
starting with the first CCW in the queue.
When the QADC encounters a CCW with the pause bit set, the queue enters the paused state after
completing the conversion specified in the CCW with the pause bit. The pause flag is set in QASR0, and
a pause interrupt may be requested. The status of the queue is shown to be paused, indicating completion
of a subqueue. The QADC then waits for another trigger event to again begin execution of the next
subqueue.
28.8.1.2 Queue Priority Schemes
Because there are two conversion command queues and only one A/D converter, a priority scheme
determines which conversion occurs. Each queue has a variety of trigger events that are intended to initiate
conversions, and they can occur asynchronously in relation to each other and other conversions in
progress. For example, a queue can be idle awaiting a trigger event; a trigger event can have occurred, but
the first conversion has not started; a conversion can be in progress; a pause condition can exist awaiting
another trigger event to continue the queue; and so on.
28-36
BQ2
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63
P
P
P
0
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
Conversion Command
Beginning of Queue 1
Beginning of Queue 2
Word (CCW) Table
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
End of Queue 1
End of Queue 2
Figure 28-22. QADC Queue Operation with Pause
Pause
Pause
Pause
Pause
Pause
Pause
•
•
•
•
•
•
Channel Select,
A/D Conversion
Sample, Hold,
Result Word Table
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Freescale Semiconductor
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