MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 233

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.4.6
The processor runs back-to-back bus cycles whenever possible. For example, when a longword read is
started on a word-size bus, the processor performs two back-to-back word read accesses. Back-to-back
accesses are distinguished by the continuous assertion of TIP throughout the cycle.
read back-to-back with a write.
Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to the type
of operations to be placed back to back. The initiation of a back-to-back cycle is not user definable.
Freescale Semiconductor
A[31:0], SIZ[1:0]
A[31:0], SIZ[1:0]
CSn, BSn
CLKOUT
Back-to-Back Bus Cycles
D[31:0]
CSn, BSn
R/W
CLKOUT
OE
TIP
TS
TA
D[31:0]
R/W
TIP
TS
TA
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 13-10. Write Cycle with Fast Termination
Figure 13-11. Back-to-Back Bus Cycles
S0
S1
S0
S2
S3
Read
S1
S4
S4
S5
Write
S0
S5
S1
S2
Write
External Interface Module (EIM)
S3
Figure 13-11
S4
S5
shows a
13-9