MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 236

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

External Interface Module (EIM)
Figure 13-15
a basic read cycle while determining that a line is being transferred. The external device uses fast
termination for subsequent transfers.
13.4.7.3 Line Write Bus Cycles
Figure 13-16
driven one clock after TS. The next pipelined burst data is driven a cycle after the write data is registered
(on the rising edge of S6). Each subsequent burst takes a single cycle. Note that as with the line read
example in
behavior of the address lines for both internal and external termination. Note that when external
termination is used, the address lines change with SIZ[1:0].
13-12
.
CSn, BSn, OE
A[31:0], SIZ[1:0]
CSn, BSn, OE
CLKOUT
SIZ[1:0]
A[31:0]
D[31:0]
CLKOUT
D[31:0]
R/W
Figure
TIP
Figure 13-15. Line Read Burst-Inhibited, Fast Termination, External Termination
shows a line access write with zero wait states. It begins like a basic write bus cycle with data
shows a burst-inhibited line read access with fast termination. The external device executes
TS
R/W
TA
TIP
TS
TA
13-12, CSn remain asserted throughout the burst transfer. This example shows the
Figure 13-14. Line Read Burst (3-2-2-2), External Termination
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
S0 S1 S2 S3
S0
S1
A[3:2] = 00
S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5
Basic
Line
Read
WS
Read
S4 S5
A[3:2] = 01
WS
Fast
Read
Read
S6
S7
A[3:2] = 10
WS
Longword
Fast
Read
Read
S8
S9
WS
A[3:2] = 11
Fast
Freescale Semiconductor
Read
Read
S10
S11
S12
S6
S13
S7