MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 495

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

25.5.8
ESTAT reflects various error conditions, some general status of the device, and is the source of three
interrupts to the host. The reported error conditions (bits 15:10) are those occurred since the last time the
host read this register. The read action clears these bits to 0.
All the bits in this register are read only, except for BOFF_INT, WAKE_INT and ERR_INT, which are
interrupt sources and can be written by the host to ‘1’.
Freescale Semiconductor
31–21
18–1
Bits
Address
20
19
0
Reset
Reset
Field
Field
R/W
R/W
FlexCAN Error and Status Register (ESTAT)
Name
MID
MID
—
—
—
31
15
Figure 25-12. Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK)
Table 25-16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions
Mask ID. MID[28:18] are used to mask standard or extended format frames.
0
1
Reserved. The IDE bit of a received frame is always compared. Its location in the mask (bit 19) is
always 1, regardless of any CPU write to this bit.
Reserved. The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
MB ID field. Note, however, that remote request frames (RTR = 1) are never received into MBs. RTR
mask bits locations in the mask (bits 20 and 0) are always read as ’0’, regardless of any CPU write
to these bits.
Mask ID. MID[17:0] are only used to mask extended format frames.
0
1
Reserved. The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
MB ID field. Note, however, that remote request frames (RTR = 1) are never received into MBs. RTR
mask bits locations in the mask (bits 20 and 0) are always read as ’0’, regardless of any CPU write
to these bits.
IPSBAR + 0x1C_0010 (RXGMASK), 0x1C_0014 (RX14MASK), 0x1C_0018 (RX15MASK)
corresponding incoming ID bit is “don’t care”.
corresponding ID bit is checked against the incoming ID bit, to see if a match exists.
corresponding incoming ID bit is “don’t care”.
corresponding ID bit is checked against the incoming ID bit, to see if a match exists.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
MID[28:18]
1111_1111_1110_1111
1111_1111_1111_1110
MID[14:0]
Description
R/W
R/W
Section 25.4.12,
21
“Interrupts.”
20
—
19
18
MID[17:15]
17
1
—
16
0
FlexCAN
25-25