MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 624

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Debug Support
These registers are accessed through the BDM port by the commands,
in
specifies the register, as shown in
30-6
Section 30.5.3.3, “Command Set
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
31
31
31
31
31
31
31
31
31
31
31
31
31
31
All debug control registers are writable from the external development system or the CPU via the WDEBUG
instruction. CSR is write-only from the programming model. It can be read or written through the BDM port
using the
All debug control registers are writable from the external development system or the CPU via the WDEBUG
instruction.
CSR is write-only from the programming model. It can be read or written through the BDM port using the
RDMREG
and
RDMREG
WDMREG
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
and
15
15
15
15
15
15
15
15
15
15
15
15
15
15
commands
WDMREG
Figure 30-4. Debug Programming Model
Table
Descriptions.” These commands contain a 5-bit field, DRc, that
commands
.
30-3.
7
7
7
.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ABLR
ABHR
CSR
DBR
DBMR
PBR
PBMR
TDR
ABLR
ABHR
BAAR
CSR
DBR
DBMR
PBR
PBMR
TDR
AATR
AATR
Address attribute trigger register
Address low breakpoint register
Address high breakpoint register
Configuration/status register
Data breakpoint register
Data breakpoint mask register
PC breakpoint register
PC breakpoint mask register
Trigger definition register
Address attribute trigger register
Address low breakpoint register
Address high breakpoint register
BDM address attribute register
Configuration/status register
Data breakpoint register
Data breakpoint mask register
PC breakpoint register
PC breakpoint mask register
Trigger definition register
WDMREG
and
Freescale Semiconductor
RDMREG
, described