MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 341

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Other registers reset when the ECR[ETHER_EN] bit is cleared (which is accomplished by a hard reset or
software to halt operation). By clearing ECR[ETHER_EN], configuration control registers such as the
TCR and RCR are not reset, but the entire data path is reset.
17.5.3
You need to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact values depend
on the particular application. The sequence is not important.
Table 17-32
Table 17-33
Freescale Semiconductor
User Initialization (Prior to Setting ECR[ETHER_EN])
defines Ethernet MAC registers requiring initialization.
defines FEC FIFO/DMA registers that require initialization.
Table 17-33. FEC User Initialization (Before ECR[ETHER_EN])
Descriptor Controller block
Table 17-31. ECR[ETHER_EN] De-Assertion Effect on FEC
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 17-32. User Initialization (Before ECR[ETHER_EN])
Register/Machine
RECV block
XMIT block
DMA block
PALR / PAUR (only needed for full duplex flow control)
RDAR
TDAR
OPD (only needed for full duplex flow control)
Clear EIR (write 0xFFFF_FFFF)
Initialize FRSR (optional)
Initialize EMRBR
TFWR (optional)
MSCR (optional)
Initialize ERDSR
Clear MIB_RAM
Initialize ETDSR
GAUR / GALR
Initialize EIMR
Description
Description
IALR / IAUR
RCR
TCR
Transmission is aborted (bad CRC
All DMA activity is terminated
Receive activity is aborted
Halt operation
Reset Value
appended)
Cleared
Cleared
Fast Ethernet Controller (FEC)
17-31