MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 540

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Queued Analog-to-Digital Converter (QADC)
28.2
28.3
This subsection describes the two modes of operation in which the QADC does not perform conversions
in a regular fashion:
28.3.1
The QDBG bit in the module configuration register (QADCMCR) governs behavior of the QADC when
the CPU enters background debug mode. When QDBG is clear, the QADC operates normally and is
unaffected by CPU background debug mode. See
(QADCMCR).
When QDBG is set and the CPU enters background debug mode, the QADC finishes any conversion in
progress and then freezes. This is QADC debug mode. Depending on when debug mode is entered, the
three possible queue freeze scenarios are:
28-2
•
•
•
•
Debug mode
Stop mode
When a queue is not executing, the QADC freezes immediately.
When a queue is executing, the QADC completes the current conversion and then freezes.
Block Diagram
Modes of Operation
Debug Mode
External
Triggers
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
MUX Address
Interface
Control
IPBUS
Digital
External
Figure 28-1. QADC Block Diagram
(18 with External MUXing)
Analog Input MUX
Command Words
8 Analog Channels
Signal Functions
64-Entry Queue
Conversion
and Digital
Section 28.6.1, “QADC Module Configuration Register
of 10-bit
(CCWs)
Reference
Inputs
Result Alignment
Analog-to-Digital
64-Entry Table
10-bit to 16-bit
Converter
of 10-bit
Results
10-bit
Analog Power
Inputs
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