W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 89

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Users should set the MDC clock setting to meet the PHY requirement (maximum 2.5MHz). Besides,
the MCLK (HCLK) frequency ranges from 10 MHz to 150 MHz (set MDC 2.5MHz).
MDCON [19]: MDC Clock On Always
Default value: 0
If this bit was set, the MDC clock will always active. Otherwise, the MDC clock will active only when
the EnMDC of MCMDR and BUSY of MIIDA are both set. In other words, the MDC clock will be turned
off after the station management command finished. This bit is only for debug.
PreSP [18]: Preamble Suppress
Default value: 0
If this bit is set, then the preamble is not sent to PHY.
BUSY [17]: Busy bit
Default value: 0
Set this bit to start a MII management read or write-operation. The MAC controller clears this bit
automatically when the operation is completed.
WR [16]: Write/Read
Default value: 0
Set this bit for a MII management write-operation. Reset the bit for a read operation.
PHYAD [12:8]: PHY Address
Default value: 0
The 5-bit address is the PHY device address to be accessed.
PHYRAD [4:0]: PHY Register Address
Default value: 0
The 5-bit address is the register address contained in the PHY to be accessed.
The MIIDA register is used to specify the control function and the data message passing for the
external physical layer device (PHY). The detail protocol and timings for the read and the write
operation, respectively, of the MII management function are illustrated as the figure below. Each bit in
the management data frame (MDIO) are synchronized at the rising edge of the MII management clock
(MDC).
MII Management Protocol
ACCESS PREAMBLE START OPERATION
WRITE
READ
1…. 1
1…. 1
01
01
MII MANAGEMENT PROTOCOL
10
01
- 86 -
PHYADDR
AAAAA
AAAAA
W90N740CD/W90N740CDG
PHYREGADDR
RRRRR
RRRRR
TA
Z0
10
16 bits
16 bits
DATA
IDLE
Z
Z