W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 152

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W90N740CDG

Manufacturer Part Number
W90N740CDG
Description
IC MCU ARM7 TDMI 176-LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
W90r
Datasheet

Specifications of W90N740CDG

Core Processor
ARM7
Core Size
16/32-Bit
Speed
80MHz
Connectivity
EBI/EMI, Ethernet, UART/USART, USB
Peripherals
DMA, POR, WDT
Number Of I /o
21
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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W90N740CD/W90N740CDG
DDSR [1]: DSR# State Change
This bit is set whenever DSR# input has changed state, and it will be reset if the CPU reads the MSR.
DCTS [0]: CTS# State Change
This bit is set whenever CTS# input has changed state, and it will be reset if the CPU reads the MSR.
Whenever any of MSR [3:0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing
MSR is a null operation (not suggested).
Time Out Register (TOR)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0xFFF8.001C
R/W
Time Out Register
TOR
0x0000.0000
7
6
5
4
3
2
1
0
TOIE
TOIC
TOIE [7]: Time Out Interrupt Enable
The feature of receiver time out interrupt is enabled only when TOR [7] = IER[0] = 1.
TOIC [6:0]: Time Out Interrupt Comparator
The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO
receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out
interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR [7] = IER [0] =
1. A new incoming data word or RX FIFO empty clears Irpt_TOUT.
Publication Release Date: Aug. 18, 2005
- 149 -
Revision A6

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