W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 32

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

If IPEN is set, an interrupt handler will normally clear IPACT at the end of the interrupt routine to allow an
alternate bus master to regain the bus; however, if IPEN is cleared, no additional action need be taken in
the interrupt handler. The IPACT bit can be read and write. Writing with “0”, the IPACT bit is cleared, but
it will be no effect as writing with “1”.
7.2.5.2. Rotate Priority Mode
In Rotate Priority Mode (PRTMOD = 1), the IPEN and IPACT bits have no function (i.e. ignore).
W90N740 used a round robin arbitration scheme ensures that all bus masters (except the External Bus
Master, it always has the first priority) have equal chance to gain the bus and that a retracted master
does not lock up the bus.
7.2.6
After power on reset, there are four Power-On setting pins to configure W90N740 system configuration.
D15 pin：Internal System Clock Select
If pin D15 is pull-down, the external clock from EXTAL pin is served as internal system clock.
If pin D15 is pull-up, the PLL output clock is used as internal system clock.
D14 pin：Little/Big Endian Mode Select
If pin D14 is pull-down, the external memory format is Big Endian mode.
If pin D14 is pull-up, the external memory format is Little Endian mode.
Internal System Clock Select
Little/Big Endian Mode Select
Boot ROM/FLASH Data Bus Width
1 (HIGHEST)
8 (LOWEST)
PRIORITY
Power-On Setting
BUS
2
3
4
5
6
7
Table 7.2.15 Bus Priorities for Arbitration in Fixed Priority Mode
POWER-ON SETTING
External Bus Master
NAT Accelerator
General DMA0
General DMA1
EMC0 DMA
EMC1 DMA
USB (Host)
ARM Core
IPACT = 0
- 29 -
W90N740CD/W90N740CDG
FUNCTION BLOCK
Publication Release Date: Aug. 18, 2005
IPEN = 1 AND IPACT = 1
External Bus Master
NAT Accelerator
General DMA0
General DMA1
EMC0 DMA
EMC1 DMA
USB (Host)
ARM Core
D [13:12]
PIN
D15
D14
Revision A6