W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 39

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.3.2
The W90N740’s SDRAM Controller contains configuration registers, timing control registers, common
control register and other logic. The SDRAM Controller provides 8/16/32 bits SDRAM interface with a
single 8/16/32 bits SDRAM device or two 8-bit devices wired to give a 16-bit data path or two 16-bit
devices wired to give a 32-bit data path. The maximum memory size of each bank is 32MB(Mbytes). One
of two banks can be connected to the SDRAM interface, so the maximum memory can be up to 64MB.
The Features of the SDRAM Controller：
7.3.2.1. SDRAM Components Supported
•
•
•
•
7.3.2.2. AHB Bus Address Mapping to SDRAM Bus
Note:
16M bit SDRAM
64M bit SDRAM
128M bit SDRAM
256M bit SDRAM
•
•
•
•
•
•
•
•
•
− 2Mx8 with 2 banks ；RA0 ~ RA10, CA0 ~ CA8
− 1Mx16 with 2 banks；RA0 ~ RA10, CA0 ~ CA7
− 8Mx8 with 4 banks；RA0 ~ RA11, CA0 ~ CA8
− 4Mx16 with 4 banks；RA0 ~ RA11, CA0 ~ CA7
− 2Mx32 with 4 banks ；RA0 ~ RA10, CA0 ~ CA7
− 16Mx8 with 4 banks；RA0 ~ RA11, CA0 ~ CA9
− 8Mx16 with 4 banks；RA0 ~ RA11, CA0 ~ CA8
− 4Mx32 with 4 banks；RA0 ~ RA11, CA0 ~ CA7
− 32Mx8 with 4 banks；RA0 ~ RA12, CA0 ~ CA9
− 16Mx16 with 4 banks；RA0 ~ RA12, CA0 ~ CA8
SDRAM Controller
8/16/32-bit data interface
Supports up to 2 external SDRAM devices and Maximum size of each device is 32MB
Programmable CAS Latency： 1、2 and 3
Fixed Burst Length： 1
Sequential burst type
Write Burst Length mode is Burst
Auto Refresh Mode and Self Refresh Mode
Adjustable Refresh Rate
Power up sequence
* indicates the signal is not used; ** indicates the signal is fixed at logic 0 and is not used;
The HADDR prefixes have been omitted on the following tables.
A14 ~ A0 are the Address pins of the W90N740 EBI interface;
A14 and A13 are the Bank Selected Signal of SDRAM.
- 36 -
W90N740CD/W90N740CDG