W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 62

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.4.4
The W90N740 data cache (D-Cache) is a 2KB two-way set associative cache. The cache organization is
64 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in
memory. The cache is designed for buffer write-through mode of operation and a least recently used
(LRU) replacement algorithm is used to select a line when no empty lines are available.
When D-Cache is disabled, the cache memory is served as 2KB On-chip RAM.
The D-Cache is always disabled on reset.
The Features of the Data Cache：
DATA CACHE OPERATION
On a data fetch, bits 9～4 of the data’s address point into the cache to retrieve the tags and data of one
set. The tags from both ways are then compared against bits 30～10 of the data’s address. If a match is
found and the matched entry is valid, then it is a cache hit. If neither tags match or the matched tag is not
valid, it is a cache miss.
7.4.4.1. Data Cache Read
Read Hit：On a cache hit, the requested word is immediately transferred to the core.
Read Miss：A line in the cache is selected to hold the data, which will be fetched from memory. The
selection algorithm gives first priority to invalid lines and if both lines are invalid the line in way zero is
selected first. If neither of the two candidate lines in the selected set is invalid, then one of the lines is
selected by the LRU algorithm to replace. The transfer begins with the aligned word containing the
missed data (critical word first), followed by the remaining word in the line, then by the word at the
beginning of the line (wraparound). As the missed word is received from the bus, it is delivered directly to
the core.
7.4.4.2. Data Cache Write
As buffer write-through mode, store operations always update memory. The buffer write-through mode is
used when external memory and internal cache images must always agree.
Write Hit：Data is written into both the cache and write buffer. The processor then continues to access
the cache, while the cache controller simultaneously downloads the contents of the write buffer to main
memory. This reduces the effective write memory cycle time from the time required for a main memory
cycle to the cycle time of the high-speed cache.
Write Miss：Data is only written into write buffer, not to the cache (write no allocate).
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Data Cache
2K bytes data cache
Two-way set associative
Four words in a cache line
LRU replacement policy
Lockable on a per-line basis
Critical word first, burst access
Buffer Write-through mode
words write buffer
Drain write buffer
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W90N740CD/W90N740CDG
Publication Release Date: Aug. 18, 2005
Revision A6