W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 31

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.2.5
The W90N740’s internal function blocks or external devices can request mastership of the system bus
and then hold the system bus in order to perform data transfers. The design of W90N740 bus allows only
one bus master at a time, a bus controller is required to arbitrate when two or more internal units or
external devices simultaneously request bus mastership. When bus mastership is granted to an internal
function block or an external device, other pending requests are not acknowledged until the previous bus
master has released the bus.
W90N740 supports two priority modes, the Fixed Priority Mode and the Rotate Priority Mode,
depends on the PRTMOD bit setting.
7.2.5.1. Fixed Priority Mode
In Fixed Priority Mode (PRTMOD = 0, default value), to facilitate bus arbitration, priorities are assigned
to each internal W90N740 function block. The bus controller arbitration requests for the bus mastership
according to these fixed priorities. In the event of contention, mastership is granted to the function block
with the highest assigned priority. These priorities are listed in Table 7.2.15.
W90N740 allows raising ARM Core priority to second if an unmasked interrupt occurred. If IPEN bit, Bit
22 of the Arbitration Control Register (ARBCON), is set to “0”, the priority of ARM Core is fixed to
lowest. If IPEN bit is set to “1” and if no unmasked interrupt request, then the ARM Core’s priority is still
lowest and the IPACT = 0, Bit 23 of the Arbitration Control Register (ARBCON) ； If there is an
unmasked interrupt request, then the ARM Core’s priority is raised to second and IPACT = 1.
EXT. MEM DATA
CPU REG DATA
OPERATION
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
SEQUENCE
SDQM [3-0]
XD WIDTH
ACCESS
TIMING
SA
SD
ED
XA
XD
Bus Arbitration
Table7.2.14 Byte access read operation with Little Endian
UUUA
31
ABCD
7 0
7 0
7 0
BA0
BA0
D
D
D
0
READ OPERATION (CPU REGISTER
UUAU
31
ABCD
7 0
7 0
7 0
BA1
BA0
C
C
C
0
WORD
31
ABCD
0
UAUU
31
ABCD
7 0
BA2
7 0
7 0
BA0
B
B
B
- 28 -
0
W90N740CD/W90N740CDG
AUUU
31
ABCD
7 0
BA3
7 0
7 0
BA0
A
A
A
0
EXTERNAL MEMORY)
XXUA
15 0
7 0
BAL
7 0
7 0
BAL
CD
D
D
D
HALF WORD
15 0
CD
XXAU
15 0
BAU
7 0
7 0
7 0
BAL
CD
C
C
C
BYTE
XXXA
7 0
7 0
7 0
7 0
7 0
BA
BA
D
D
D
D
D