ADUC7032BSTZ-8V-RL Analog Devices Inc, ADUC7032BSTZ-8V-RL Datasheet - Page 85

• Manufacturer Part Number: ADUC7032BSTZ-8V-RL
• Description: IC BATTERY SENSOR PREC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8V-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: ADUC7032BSTZ-8V-RLCT

Preliminary Technical Data
Timer3 Clear Register :
Name :
Address :
Default Value :
Access :
Function :
Timer3 Control Register :
Name :
Address :
Default Value :
Access :
Function :
Bit
16-9
8
7
6
5
4
3-2
1
0
Description
These bits are reserved and should be written as 0 by user code
Count Up/Down Enable
Set by user code to configure Timer3 to count up
Cleared by user code to configure Timer3 to count down.
Timer3 Enable
Set by user code to enable Timer 3
Cleared by user code to disable Timer 3. .
Timer3 Operating Mode
Set by user code to configure Timer3 to operate in periodic mode
Cleared by user to configure Timer3 to operate in free-running mode.
Watchdog Timer Mode Enable
Set by user code to enable watchdog mode
Cleared by user code to disable watchdog mode.
This bit is reserved and should be written as 0 by user code
Timer3 Clock(32.768kHz) Pre-Scalar
00
01
10
11
Watchdog Timer IRQ Enable
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0
Cleared by user code to disable the IRQ option.
PD_OFF
Set by the user code to stop Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR.
Cleared by the user code to enable Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR.
Source clock / 1 ( Default )
Source clock / 16
Source clock / 256
Reserved
T3CLRI
0xFFFF036C
0x00
Write Only
This 16-bit, write-only MMR is written
T3CON
0xFFFF0368
0x00
Read/Write Once Only
The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 47.
Table 47 : T3CON MMR Bit Definition
Rev. PrD | Page 85 of 128
(with any value) by user code to refresh(reload) Timer3 in
watchdog mode to prevent a watchdog timer reset event. This
register must be written with a specific value (generated by user
code, based on a polynomial equation) to refresh the watchdog
timer and prevent a watchdog reset.
ADuC7032