ADUC7032BSTZ-8V-RL Analog Devices Inc, ADUC7032BSTZ-8V-RL Datasheet
ADUC7032BSTZ-8V-RL
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ADUC7032BSTZ-8V-RL Summary of contents
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Preliminary Technical Data FEATURES High Precision ADCs Dual Channel, Simultaneous Sampling, 16-Bit Σ−∆ ADCs Third Independent ADC for Temperature Sensing Programmable ADC throughput from 1Hz to 8KHz On-Chip 5ppm/°C Voltage Reference Current Channel Fully differential, Buffered Input Programmable Gain 1 ...
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Preliminary Technical Data TABLE OF CONTENTS TABLE OF CONTENTS................................................... 2 ADUC7032 DATASHEET TABLES................................. 5 ADUC7032 DATASHEET FIGURES .............................. 7 ADUC7032SPECIFICATIONS ........................................ ............................................ 8 LECTRICAL PECIFICATIONS T S ................................................. 15 IMING PECIFICATIONS SPI Timing Specifications........................................... 15 LIN Timing ...
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Preliminary Technical Data PLLCON Pre-write Key PLLKEY1: ........................... 70 PLLCON Register : .................................................... 70 POWCON Pre-write Key POWKEY0: ....................... 70 POWCON Pre-write Key POWKEY1: ....................... 70 POWCON Register : .................................................. 71 AD C7032 OWER ...
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Preliminary Technical Data System Serial ID Register 0: .................................... 125 System Serial ID Register 1: .................................... 126 System Kernel Checksum: ........................................ 126 System Identification FEE0ADR: .............................127 OUTLINE DIMENSIONS.............................................128 Rev. PrD | Page 4 of 128 ADuC7032 ...
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Preliminary Technical Data ADUC7032 DATASHEET TABLES Table 1 : ADUC7032—SPECIFICATIONS Table 2 : SPI Master Mode Timing (PHASE Mode = 1) Table 3 : SPI Master Mode Timing (PHASE Mode = 0) Table 4 : SPI Slave Mode Timing (PHASE ...
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Preliminary Technical Data Table 59 : GP1CLR MMR Bit Descriptions Table 60 : GP2CLR MMR Bit Descriptions Table 61: HVCON MMR Write Bit Designations Table 62: HVCON MMR Read Bit Designations Table 63: HVDAT MMR Bit Designations Table 64: HVCFG0 ...
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Preliminary Technical Data ADUC7032 DATASHEET FIGURES Figure 1: ADuC7032 Functional Block Diagram..........................1 Figure 2. SPI Master Mode Timing (PHASE Mode = 1)............15 Figure 3. SPI Master Mode Timing (PHASE Mode = 0)............16 Figure 4. SPI Slave Mode Timing (PHASE Mode ...
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Preliminary Technical Data ADUC7032SPECIFICATIONS ELECTRICAL SPECIFICATIONS (V =3.5V to18V 1.2 V Internal Reference REF precision oscillator, All specifications T Parameter Test Conditions/Comments ADC SPECIFICATIONS 1 Chop Off, ADC Normal Operating Mode Conversion Rate Chop On, ADC ...
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Preliminary Technical Data Parameter Test Conditions/Comments Temperature Channel 1 No Missing Codes Valid at all ADC Update Rates 1 Integral Nonlinearity 3, 5,16, 17 Offset Error Chop Off , 1 LSB 1, 3 Offset Error Chop On Offset Error Drift ...
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Preliminary Technical Data Parameter Test Conditions/Comments RESISTIVE ATTENUATOR Divider Ratio Resistor Mismatch Drift ADC Ground Switch Resistance Direct path to ground 20kΩ Resistor selected Input Current 27 TEMPERATURE SENSOR Accuracy MCU in power down or standby mode MCU in power ...
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Preliminary Technical Data Parameter Test Conditions/Comments 1 LOGIC INPUTS All Logic inputs VINL, Input Low Voltage VINH, Input High Voltage 1 CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage XTAL1 Capacitance XTAL2 Capacitance ON-CHIP ...
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Preliminary Technical Data Parameter Test Conditions/Comments 31 I Control Unit disconnected from ground LIN_NO_GND V 1 LIN Receiver Dominant State, VDD > 7.0V LIN_DOM 1 V LIN Receiver Recessive State, VDD > 7.0V LIN_REC 1 V LIN Receiver Centre Voltage, ...
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Preliminary Technical Data Parameter Test Conditions/Comments LIN V2.0 Specification Bus Load Conditions ( C 1nF||1kΩ ; 6.8nF|| 660 Ω ; 10nF || 500Ω D1 Duty Cycle 1 D2 Duty Cycle 2 Wake R 1 VDD Supply Voltage Range for which ...
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Preliminary Technical Data Parameter Test Conditions/Comments 1 I – MCU Powered Down ADC Low Power-Plus Mode, measured over an DD ambient temperature range of -10°C to +40°C (Continuous ADC Conversion ) I – MCU Powered Down Average Current, Measured with ...
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Preliminary Technical Data TIMING SPECIFICATIONS SPI Timing Specifications Parameter Description t SCLOCK low pulsewidth SL t SCLOCK high pulsewidth SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data input ...
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Preliminary Technical Data Parameter Description t SCLOCK low pulsewidth SL t SCLOCK high pulsewidth SH t Data output valid after SCLOCK edge DAV t Data output setup before SCLOCK edge DOSU t Data input setup time before SCLOCK edge DSU ...
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Preliminary Technical Data Parameter Description SCLOCK edge CS t SCLOCK low pulsewidth SL t SCLOCK high pulsewidth SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data ...
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Preliminary Technical Data Parameter Description SCLOCK edge CS t SCLOCK low pulsewidth SL t SCLOCK high pulsewidth SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data ...
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Preliminary Technical Data LIN Timing Specifications Figure 6 : LIN V1.3 Timing Specification Rev. PrD | Page 19 of 128 ADuC7032 ...
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Preliminary Technical Data RECESSIVE TRANSMIT INPUT TO TRANSMITTING NODE DOMINANT TH REC (MAX) TH DOM (MAX) V SUP (TRANSCEIVER SUPPLY OF TRANSMITTING NODE) TH REC (MIN) TH DOM (MIN) RxD (OUTPUT OF RECEIVING NODE 1) RxD (OUTPUT OF RECEIVING NODE ...
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Preliminary Technical Data SPECIFICATION TERMINOLOGY CONVERSION RATE: The conversion rate specifies the rate at which an output result is available from the ADC, once the ADC has settled. The sigma-delta conversion techniques used on this part mean that while the ...
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 6. Absolute Maximum Ratings (T Parameter AGND to DGND to VSS to IO_VSS VBAT to AGND V to VSS VSS for 1 second DD LIN to IO_VSS WU to IO_VSS ...
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Preliminary Technical Data PIN FUNCTION DESCRIPTIONS Pin# Mnemonic RESET 1 2 GPIO_5/IRQ1/RxD 3 GPIO_6/TxD 4 GPIO_7/IRQ4 5 GPIO_8/ IRQ5 6 TCK 7 TDI 8 DGND TDO 11 NTRST 12 TMS Table 7: Pin Function Descriptions * Type ...
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Preliminary Technical Data Pin# Mnemonic 13 VBAT 14 VREF 15 GND_SW VTEMP 19 IIN+ 20 IIN- 21 AGND 22 AGND REG_AVDD GPIO_0/IRQ0/ GPIO_1/SCLK 29 GPIO_2/MIS0 30 ...
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Preliminary Technical Data Pin# Mnemonic 33 REG_DVDD 34 DGND 35 DGND 36 XTAL1 37 XTAL2 VDD VSS Reserved 47 IO_VSS 48 LIN * I = ...
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Preliminary Technical Data ADUC7032 GENERAL DESCRIPTION The ADuC7032 is a complete, system solution for battery monitoring in 12V automotive applications. The device integrates all of the required features to precisely and intelligently monitor, process and diagnose 12V battery parameters including ...
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Preliminary Technical Data EmbeddedICE (I) The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers which allow non intrusive user code debugging. These registers are controlled through the JTAG test ...
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Preliminary Technical Data Interrupt latency The worst case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer, plus the time for the longest instruction to complete (the longest instruction is an ...
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Preliminary Technical Data Remap The ARM exception vectors are all situated at the bottom of the memory array, from address 0x00000000 0x00000020. By default, after a reset, the Flash/EE memory is logically mapped to address 0x00000000 possible to ...
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Preliminary Technical Data ADUC7032 RESET There are four kinds of reset: external reset, Power-on-reset, watchdog reset and software reset. The RSTSTA register indicates the source of the last reset and can also be written by user code to initiate a ...
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Preliminary Technical Data FLASH/EE MEMORY AND THE ADUC7032 The ADuC7032 incorporates Flash/EE memory technology on- chip to provide the user with non-volatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it ...
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Preliminary Technical Data - FEExPRO ( 1): A buffer of the FEEHIDE register, which is used to store the FEEHIDE value automatically downloaded to the FEEHIDE registers on subsequent reset and power-on events. NOTE: User ...
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Preliminary Technical Data Command Sequence for executing a Mass Erase Giving the significance of the ‘Mass Erase’ command, a specific code sequence must be executed to initiate this operation. 1. Set bit 3 in FEExMOD. 2. Write 0xFFC3 in FEExADR ...
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Preliminary Technical Data FEE0MOD and FEE1MOD Registers : Name : FEE0MOD and FEE1MOD Address : 0xFFFF0E04 and 0xFFFF0E84 Default Value (both registers) : 0x00 Read/Write Access : These registers are written by user code to configure the mode of operation ...
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Preliminary Technical Data Block0, Flash/EE Memory Protection Registers : Name : FEE0HID and FEE0PRO Address : 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C (for FEE0PRO) Default Value (both registers) : 0xFFFFFFFF Read/Write Access Access : These registers are written by user code ...
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Preliminary Technical Data In Summary, there are three levels of protection: - Temporary Protection can be set and removed by writing directly into FEExHID MMR. This register is volatile and therefore protection will only be in place while the part ...
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Preliminary Technical Data CODE EXECUTION TIME FROM SRAM AND FLASH/EE This chapter describes SRAM and Flash/EE access times during execution for applications where execution time is critical. Execution from SRAM Fetching instructions from SRAM takes one clock cycle as the ...
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Preliminary Technical Data ADUC7032 KERNEL The ADuC7032 features an on-chip Kernel resident in the top 2k of the Flash/EE Code space. After any reset event, this kernel copies the factory calibrated data from the manufacturing data space, into the various ...
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Preliminary Technical Data PAGE ERASED? 0x14 = 0xffffffff YES LIN COMMAND INITIALIZE ON-CHIP PERIPHERALS TO FACTORY CALIBRATED STATE NO YES JTAG MODE? NTRST = 1 NO YES KEY PRESENT? 0x14 = 0x27011970 NO CHECKSUM PRESENT? 0x14 = CHECKSUM NO FLAG ...
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Preliminary Technical Data MEMORY MAPPED REGISTERS The Memory Mapped Register (MMR) space is mapped into the top 4kBytes of the MCU memory space and accessed by indirect addressing, load and store commands, through the ARM7 banked registers. An outline of ...
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Preliminary Technical Data Address Name Byte IRQ address base = 0xFFFF0000 0x0000 IRQSTA 4 1 0x0004 IRQSIG 4 0x0008 IRQEN 4 0x000C IRQCLR 4 0x0010 SWICFG 4 0x0100 FIQSTA 4 1 0x0104 FIQSIG 4 0x0108 FIQEN 4 0x010C FIQCLR 4 ...
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Preliminary Technical Data 2 0x0368 T3CON 2 2 0x036C T3CLRI 1 PLL base address = 0xFFFF0400 0X0400 PLLSTA 4 0x0404 POWKEY0 4 0x0408 POWCON 1 0x040C POWKEY1 4 0x0410 PLLKEY0 4 0x0414 PLLCON 1 0x0418 PLLKEY1 4 0x042C OSC0TRM 1 ...
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Preliminary Technical Data 0x0554 ADC0TCL 1 0x0558 ADC0THV 1 0x055C ADC0ACC 4 0x0560 ADC0ATH 4 2 0x057C ADCREF 4 UART BASE ADDRESS = 0XFFFF0700 0x0700 COMTX 1 COMRX 1 COMDIV0 1 0x0704 COMIEN0 1 COMDIV1 1 0x0708 COMIID0 1 0x070C ...
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Preliminary Technical Data 3 0x0D 38 GP1CLR 4 3 0x0D 40 GP2DAT 4 3 0x0D 44 GP2SET 4 3 0x0D 48 GP2CLR 4 Flash/EE base address = 0xFFFF0E00 0x0E00 FEE0STA 1 0x0E04 FEE0MOD 2 0x0E08 FEE0CON 1 0x0E0C FEE0DAT 2 ...
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Preliminary Technical Data 16-BIT Σ−∆ ANALOG TO DIGITAL CONVERTERS The ADuC7032 incorporates three independent sigma-delta ADCs namely, the Current Channel ADC (I-ADC), the Voltage Channel ADC (V-ADC) and the Temperature Channel ADC (T-ADC). These precision measurement channels integrate on- chip ...
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Preliminary Technical Data VOLTAGE CHANNEL ADC (V-ADC) This ADC is intended to convert battery voltage As with the Current Channel ADC described previously, this ADC employs an identical sigma-delta conversion technique, including a modified Sinc3 low-pass filter to give a ...
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Preliminary Technical Data ADC GROUND SWITCH The ADuC7032 features an integrated ground switch pin, GND_SW located on Pin15. This switch allows the user to dynamically disconnect ground from external devices. It allows either a direct connection to ground ...
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Preliminary Technical Data ADC NOISE PERFORMANCE TABLES Table 19, Table 20 and Table 21 below show the output RMS noise in μV for some typical output update rates on the I and V/T ADCs. The numbers are typical and are ...
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Preliminary Technical Data ADC MMR INTERFACE The ADC is controlled and configured via a number of MMRs that are described in detail in the following pages: ADC Status Register : ADCSTA Name : Address : 0xFFFF0500 0x0000 Default Value : ...
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Preliminary Technical Data 4 Current Channel ADC Comparator Threshold This bit is only valid if the Current Channel ADC comparator is enabled via the ADCCFG MMR. This bit is set by hardware if the absolute value of the I-ADC conversion ...
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Preliminary Technical Data ADC Mode Register : Name : ADCMDE Address : 0xFFFF0508 Default Value : 0x00 Read/Write Access : The ADC Mode MMR is an 8-bit register that configures the mode .of operation of the ADC sub-system Function : ...
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Preliminary Technical Data ADC System Zero-Scale Calibration In this mode, an zero-scale calibration is performed on enabled ADC channels against an external zero-scale voltage driven at the ADC input pins. The calibration is carried out at the ...
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Preliminary Technical Data Current Channel ADC Gain Select (note, nominal I-ADC Full-scale Input Voltage = (Vref/GAIN I-ADC Gain = I-ADC Gain = I-ADC Gain =4 ...
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Preliminary Technical Data Temperature Channel ADC Control Register : Name : ADC2CON Address : 0xFFFF0514 Default Value : 0x0000 Access : Read/Write Function : The Temperature Channel ADC Control MMR is an 16-bit register that is used to configure the ...
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Preliminary Technical Data ADC Filter Register : Name : ADCFLT Address : 0xFFFF0518 Default Value : 0x0007 Read/Write Access : The ADC Filter MMR is an 16-bit register that controls the speed and resolution of the on-chip ADCs. Function : ...
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Preliminary Technical Data Chop Running Enabled Average Yes No Yes Yes N/A *An additional time of 60us per enabled ADC is required before the first ADC result is available. SF Table 28 : ADC Conversion ...
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Preliminary Technical Data ADC Configuration Register : Name : ADCCFG Address : 0xFFFF051C Default Value : 0x00 Read/Write Access : The 8-bit ADC Configuration MMR controls extended functionality related to the on-chip ADCs. Function : Bit Description 7 Analog Ground ...
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Preliminary Technical Data Current Channel ADC Data Register : Name : ADC0DAT Address : 0xFFFF0520 Default Value : 0x0000 Read Only Access : This ADC Data MMR holds the 16-bit Function : conversion result from the I-ADC. The ADC will ...
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Preliminary Technical Data Current Channel ADC Gain Calibration Register : Name : ADC0GN Address : 0xFFFF053C Default Value : Part Specific, factory programmed Read/Write Access : Function : This Gain MMR holds a 16-bit gain calibration coefficient for scaling the ...
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Preliminary Technical Data bit is set in the ADCSTA MMR generating an ADC interrupt. The I-ADC Comparator Threshold bit is asserted as soon as the ADC0THV=ADC0TCL. Current Channel ADC Threshold Count Register: Name : ADC0THV Address : 0xFFFF0558 Default Value ...
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Preliminary Technical Data ADC Normal Power Mode In Normal Mode, the Current and Voltage/Temperature channels are fully enabled. The ADC modulator clock is 512KHz and enables the ADCs to provide regular conversion results at a rate of between 4Hz and ...
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Preliminary Technical Data By default the ADCFLT = 0x07 which configures the ADCs for a through-put of 1.0KHz with all other filtering options (Chop, Running Average, Averaging Factor and Sinc3 Modify) being disabled. A typical filter response based on this ...
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Preliminary Technical Data 0 H(f) [dB] -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 100 120 Figure 23 Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x961F) Changing SF to 0x1D and setting ...
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Preliminary Technical Data ADC Calibration As described in detail in the top level diagrams at the start of this section, the signal flow through all ADC Channels can be described in simple terms as: An Input-voltage is applied through an ...
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Preliminary Technical Data A factory or end-of-line calibration for the I-ADC would be a 2-step procedure: 1. Apply 0A current. Configure the ADC in the required PGA setting etc. and write to ADCMDE[2:0] to perform a System Zero-Scale Calibration. This ...
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Preliminary Technical Data Temperature ADC Diagnostics The ADuC7032 features the capability to detect Open Circuit conditions on the Temperature Channel inputs. This is accomplished using the two current sources on VTEMP+ and GND_SW, which is controlled via ADC2CON[14,13]. The use ...
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Preliminary Technical Data POWER SUPPLY SUPPORT CIRCUITS The ADuC7032 incorporates an on-chip Low Drop-Out(LDO) regulator which is driven directly from the battery voltage to generate a 2.6V internal supply. This 2.6V supply is then used as the supply voltage for ...
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Preliminary Technical Data ADUC7032 SYSTEM CLOCKS The ADuC7032 integrates a highly flexible clocking system, which may be clocked from one of three sources integrated on-chip precision oscillator 2. An integrated on-chip low power oscillator external watch ...
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Preliminary Technical Data The operating mode, clocking mode and programmable clock divider are controlled via two MMRs, PLLCON and POWCON, and the status of the PLL is indicated by PLLSTA. PLLCON controls the operating mode of the clock system while ...
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Preliminary Technical Data PLLCON Pre-write Key PLLKEY0: Name : PLLKEY0 Address : 0xFFFF0410 Default Value : 0x00000000 Access : Write Only Key: 0x000000AA Function : PLLCON is a keyed register that requires a 32 Bit key value to be written ...
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Preliminary Technical Data POWCON Register : Name : POWCON Address : 0xFFFF0408 Default Value : 0x079 Access : Read/Write Function : This 8-bit register allows user code dynamically enter various Low Power modes and modify the CD divider which controls ...
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Preliminary Technical Data ADUC7032 LOW POWER CLOCK CALIBRATION The low power 131kHz oscillator may be calibrated using either the precision 131kHz oscillator external 32.768KHz watch crystal. Two dedicated calibration counters and an oscillator trim register are used to ...
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Preliminary Technical Data OSC0TRM Register : Name : OSC0TRM Address : 0xFFFF042C Default Value : 0x08 Access : Read/Write Function : This 8-bit register controls the Low Power Oscillator Trim Bit Description 7-4 Reserved and should be written as zeros ...
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Preliminary Technical Data OSC0STA Register : Name : OSC0STA Address : 0xFFFF0444 Default Value : 0x00 Access : Read Access only Function : This 8-bit register reflects the status of the Low Power Oscillator Calibration routine Bit Description 31-4 Reserved ...
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Preliminary Technical Data PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 15 interrupt sources on the ADuC7032 which are controlled by the Interrupt Controller. Most interrupts are generated from the on-chip peripherals such as the ADC, UART, etc.. The ARM7TDMI CPU ...
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Preliminary Technical Data IRQ The IRQ is the exception signal to enter the IRQ mode of the processor used to service general purpose interrupt handling of internal and external events. The four 32-bit registers dedicated to IRQ are: ...
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Preliminary Technical Data TIMERS The ADuC7032 features four general purpose Timer/Counters: - Timer0, or Life-Time Timer - Timer1, - Timer2 or Wake-up Timer, - Timer3 or Watchdog Timer. The four timers in their normal mode of operation may either be ...
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Preliminary Technical Data TIMER0 – LIFE-TIME TIMER Timer0 is a general purpose 48-bit count-up 16-bit count up/down timer with a programmable prescalar. Timer0 may be clocked from either the Core clock, the Low Power 32.768kHz Oscillator, the Precision ...
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Preliminary Technical Data Timer0 Control Register : T0CON Name : Address : 0xFFFF030C Default Value : 0x00 Access : Read/Write Only Function : The 17-bit MMR configures the mode of operation of Timer0 Bit Description 31-18 Reserved This bit is ...
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Preliminary Technical Data TIMER1 Timer1 is a 32-bit general purpose timer, count-down or count- up, with a programmable pre-scalar. The pre-scalar source can be the Low Power 32.768kHz Oscillator, the core clock, or from one of two external GPIO. This ...
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Preliminary Technical Data Timer1 Capture Register : Name : T1CAP Address : 0xFFFF0330 Default Value : 0x00 Access : Write Only Function : This is a 32-bit register which holds the 32- bit value captured by an enabled IRQ event. ...
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Preliminary Technical Data TIMER2 - WAKE-UP TIMER Timer2 is a 32-bit wake-up timer, count-down or count-up, with a programmable prescalar. The pre-scalar is clocked directly from clock sources, namely, the Core Clock (default selection), the Low Power ...
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Preliminary Technical Data Timer2 Control Register : T2CON Name : Address : 0xFFFF0348 Default Value : 0x0000 Access : Read/Write Only Function : This 32-bit MMR configures the mode of operation of Timer2 Bit Description 31-11 Reserved 10-9 Clock Source ...
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Preliminary Technical Data TIMER3 - WATCHDOG TIMER Timer3 has two modes of operation, normal mode and watchdog mode. The Watchdog timer is used to recover from an illegal software state. Once enabled it requires periodic servicing to prevent it from ...
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Preliminary Technical Data Timer3 Clear Register : Name : T3CLRI Address : 0xFFFF036C Default Value : 0x00 Access : Write Only This 16-bit, write-only MMR is written Function : Timer3 Control Register : T3CON Name : Address : 0xFFFF0368 0x00 ...
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Preliminary Technical Data GENERAL PURPOSE I/O The ADuC7032 features 9 General Purpose bi-directional I/O pins (GPIO). In general, many of the GPIO pins have multiple functions which can be configured by user code. By default, the GPIO pins are configured ...
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Preliminary Technical Data GPIO PIN PORT SIGNAL GPIO0 P0.0 IRQ0 GPIO1 P0.1 GPIO2 P0.2 GPIO3 P0.3 GPIO4 P0.4 1 P0.5 1 P0.6 GPIO5 P1.0 IRQ1 GPIO6 P1.1 GPIO7 P2.0 IRQ4 GPIO8 P2.1 IRQ5 2 2 GPIO11 P2 GPIO12 ...
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Preliminary Technical Data GPIO Port0 Control Register : GP0CON Name : Address : 0xFFFF0D00 Default Value : 0x00000000 Access : Read/Write Function : The 32-bit MMR selects the pin function for each Port0 pin. Bit Description 31-29 Reserved These bits ...
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Preliminary Technical Data GPIO Port1 Control Register : Name : GP1CON Address : 0xFFFF0D04 Default Value : 0x00000000 Access : Read/Write Function : The 32-bit MMR selects the pin function for each Port1 pin. Bit Description 31-5 Reserved These bits ...
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Preliminary Technical Data 16 GPIO11 Function Select Bit This bit is cleared user code to internally disable the LIN input data path. In this configuration GPIO11 is used to support diagnostic read-back on all external high-voltage I/O ...
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Preliminary Technical Data 20 Port 0.4 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.4. 19 Port 0.3 Data Output The value written to this bit appears directly on the GPIO pin ...
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Preliminary Technical Data GPIO Port2 Data Register : Name : GP2DAT Address : 0xFFFF0D40 Default Value : 0x00000000 Access : Read/Write This 32-bit MMR configures the direction of the GPIO pins assigned to Port2 (see Table 48). This register also ...
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Preliminary Technical Data 1 Port 2.1 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.1. User code should write 0 to this bit. 0 Port 2.0 Data Input This ...
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Preliminary Technical Data GPIO Port1 Set Register : GP1SET Name : Address : 0xFFFF0D34 Default Value : 0x00000000 Access : Read/Write This 32-bit MMR allow user code to individually bit address external GPIO pins to set them high only. Function ...
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Preliminary Technical Data GPIO Port0 Clear Register : Name : GP0CLR Address : 0xFFFF0D28 Default Value : 0x00000000 Access : Read/Write This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only. Function ...
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Preliminary Technical Data GPIO Port2 Clear Register : Name : GP2CLR Address : 0xFFFF0D48 Default Value : 0x00000000 Access : Read/Write Function : This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low ...
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Preliminary Technical Data HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE The ADuC7032 integrates a number of high voltage circuit functions which are controlled and monitored via a registered interface consisting of 2 MMRs, namely, HVCON and HVDAT. The HVCON register acts as ...
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Preliminary Technical Data High Voltage Interface Control Register : Name : HVCON Address : 0xFFFF0804 Default Value : 0x00 Access : Read/Write Function : This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes ...
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Preliminary Technical Data High Voltage Data Register: Name : HVDAT Address : 0xFFFF080C Default Value : 0x00 Read/Write Access : Function : HVDAT is a 12-bit register that is used to hold data to be written indirectly to and read ...
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Preliminary Technical Data High Voltage Configuration0 Register : HVCFG0 Name : Address : Indirectly addressed via the HVCON high voltage interface Default Value : 0x00 Access : Read/Write Function : This 8-bit register controls the function of high voltage circuits ...
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Preliminary Technical Data High Voltage Configuration1 Register : HVCFG1 Name : Address : Indirectly addressed via the HVCON high voltage interface Default Value : 0x00 Access : Read/Write Function : This 8-bit register controls the function of high voltage circuits ...
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Preliminary Technical Data High Voltage Interrupt Status Register : Name : HVSTA Address : Indirectly addressed via the HVCON high voltage interface Default Value : 0x00 Read Only. This register should only be read on a high voltage interrupt. Access ...
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Preliminary Technical Data High Voltage Monitor Register : HVMON Name : Address : Indirectly addressed via the HVCON high voltage interface Default Value : 0x00 Access : Read Only Function : This 8-bit read only register reflects the current status ...
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Preliminary Technical Data WAKE-UP(WU) The Wake Up pin is a high voltage GPIO controlled via HVCON and HVDAT. Wake-Up(WU) Pin Circuit Description The WU pin is configured by default as an output with an internal 10KΩ pull-down resistor and high ...
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Preliminary Technical Data HANDLING INTERRUPTS FROM THE HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE An interrupt controller is also integrated with the high voltage circuits. If enabled via IRQEN[16], one of 5 high voltage sources can assert the high voltage interrupt (IRQ3) ...
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Preliminary Datasheet UART SERIAL INTERFACE The ADuC7032 features a 16450 compatible UART. The UART is a full-duplex Universal Asynchronous Receiver/Transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on ...
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Preliminary Technical Data UART REGISTER DEFINITION The UART interface consists of 9 registers namely: - COMTX: 8-bit transmit register - COMRX: 8-bit receive register - COMDIV0: divisor latch (low byte) COMTX, COMRX and COMDIV0 share the same address location. COMTX ...
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Preliminary Technical Data UART Control Register 0: COMCON0 Name : Address : 0xFFFF070C Default Value : 0x00 Access : Read/Write Function : This 8-bit register controls the operation of the UART in conjunction with COMCON1 Bit Name Description 7 DLAB ...
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Preliminary Technical Data UART Control Register 1: COMCON1 Name : Address : 0xFFFF0710 Default Value : 0x00 Access : Read/Write Function : This 8-bit register controls the operation of the UART in conjunction with COMCON0 Bit Name Description 7-6 UART ...
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Preliminary Datasheet UART Interrupt Enable Register 0: Name : COMIEN0 Address : 0xFFFF0704 Default Value : 0x00 Read/Write Access : Function : The 8-bit register enables/disables the individual UART interrupt sources. Bit Name Description 7-3 Reserved and should be written ...
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Preliminary Technical Data UART Fractional Divider Register: COMDIV2 Name : Address : 0xFFFF072C Default Value : 0x0000 Access : Read/Write Function : This 16-bit register controls the operation of the ADuC7032’s fractional divider Bit Name Description 15 FBEN Fractional baud ...
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Preliminary Technical Data SERIAL PERIPHERAL INTERFACE The ADuC7032 features a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface which allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full ...
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Preliminary Technical Data SPI Control Register : SPICON Name : Address : 0xFFFF0A10 Default Value : 0x0000 Access : Read/Write Function : The 16-bit MMR configures the Serial Peripheral Interface. Bit Description 15-13 Reserved and should be written as zero ...
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Preliminary Technical Data SPI Status Register : SPISTA Name : Address : 0xFFFF0A00 Default Value : 0x00 Access : Read Only Function : The 8-bit MMR represents the current status of the Serial Peripheral Interface. Bit Description 7-6 Reserved 5 ...
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Preliminary Technical Data LIN (LOCAL INTERCONNECT NETWORK ) INTERFACE The ADuC7032 features a high voltage physical interface between the ARM7 MCU core and an external LIN bus. The LIN interface operates as a slave only interface, operating from 1-20KBaud, and ...
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Preliminary Technical Data LIN Hardware Synchronization Status Register : Name : LHSSTA Address : 0xFFFF0780 Default Value : 0x00 Read Only Access : The LHS Status register is an 8-bit register whose bits reflect the current operating status of the ...
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Preliminary Technical Data LIN Hardware Synchronization Control Register 0: Name : LHSCON0 Address : 0xFFFF0784 Default Value : 0x0000 Read/Write Access : The LHS Control register is a 16-bit register that in conjunction with the LHSCON1 register is used to ...
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Preliminary Technical Data 0 LHS Reset Bit This bit is cleared user code to enable the LHS logic to function normally This bit is set user code to reset all LHS logic to default ...
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Preliminary Technical Data LIN Hardware Break Timer1 Register : Name : LHSVAL1 Address : 0xFFFF0790 Default Value : 0x000(read) or 0x047(write) Read/Write Access : Function : When user code reads this location, the 12-bit value returned is the value of ...
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Preliminary Technical Data LIN Frame Break Symbol As shown in Figure 40, the LIN “break” symbol is used to signal the start of a new frame. It lasts at least 13 bit periods and a slave must be able to ...
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Preliminary Technical Data LIN Frame Data Byte The data byte frame carries between one and eight bytes of data. The number of bytes contained in the frame will be START BIT LIN Frame Data Transmission and Reception Once the Break ...
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Preliminary Technical Data Example LIN Hardware Synchronization Routine Consider the following C-Source Code LIN Initialization Routine. void LIN_INIT(void ) { char HVstatus; GP2CON = 0x110000; // Enable LHS on GPIO Pins LHSCON0 = 0x1; // Reset LHS Interface do{ HVDAT ...
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Preliminary Technical Data LHSVAL1 BREAK LHSVAL0 STARTS RESET AND COMPARE COUNTING STARTS INTERRUPT COUNTING GENERATED T START BIT LHSVAL1 = 0x3F LIN Diagnostics The ADuC7032 features the capability to non-intrusively monitor the current state of the LIN pin. This read ...
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Preliminary Technical Data ADUC7032 ON-CHIP DIAGNOSTICS The ADuC7032 integrates multiple diagnostic support circuits on-chip. These circuits allow the device to test core digital functionality, analog front-end and high-voltage I/O ports in-circuit. ADC Diagnostics Internal Test Voltage The current channel can ...
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Preliminary Technical Data PART IDENTIFICATION Two registers mapped into the MMR space are intended to allow user code identify and trace, manufacturing lot ID information, part ID number, silicon mask revision and kernel System Serial ID Register 0: Name : ...
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Preliminary Technical Data System Serial ID Register 1: Name : SYSSER1 Address : 0xFFFF023C Default Value : 0x00000000(Updated by kernel at power-on) Read/Write Access : At power-on, this 32-bit register will hold the values of the part ID number, silicon ...
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Preliminary Technical Data System Identification FEE0ADR: Name : FEE0ADR Address : 0xFFFF0E10 Default Value : Non Zero Read/Write Access Access : This 16-bit register dictates the address upon which any Flash/EE command executed via FEExCON will act upon. Function : ...
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Preliminary Technical Data OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 0.05 VIEW A ROTATED 90° CCW Figure 45 : 48-Lead, Plastic Quad Flat Pack, (LQFP-48), Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0.45 0.20 0.09 7° 3.5° 12 0° SEATING ...