UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 824
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
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17.6.4 SBF reception
UCnCTL0.UCnRXE bit to 1.
bit detection is performed.
rate.
completion interrupt request signal (INTUCnR) is output. The UCnOPT0.UCnSRF bit is automatically cleared and
SBF reception ends. Error detection for the UCnSTR.UCnOVE, UCnSTR.UCnPE, and UCnSTR.UCnFE bits is
suppressed and UART communication error detection processing is not performed. Moreover, data transfer of the
UARTCn reception shift register and UCnRX register is not performed and FFH, the initial value, is held. If the SBF
width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the SBF
reception mode is returned to. The UCnSRF bit is not cleared at this time.
822
The reception wait status is entered by setting the UCnCTL0.UCnPWR bit to 1 and then setting the
The SBF reception wait status is set by setting the SBF reception trigger (UCnOPT0.UCnSRT bit) to 1.
In the SBF reception wait status, similarly to the UART reception wait status, the RXDCn pin is monitored and start
Following detection of the start bit, reception is started and the internal counter counts up according to the set baud
When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception
Cautions 1. If SBF is transmitted during a data reception, a framing error occurs.
(a) Normal SBF reception (detection of stop bit in more than 10.5 bits)
(b) SBF reception error (detection of stop bit in 10.5 or fewer bits)
Remark
2. Do not set the SBF reception trigger bit (UCnSRT) and SBF transmission trigger bit (UCnSTT)
INTUCnR
interrupt
RXDCn
UCnSRF
to 1 during an SBF reception (UCnSRF = 1).
RXDCn
UCnSRF
INTUCnR
interrupt
n = 0 to 5 (V850ES/JH3-E)
n = 0 to 7 (V850ES/JJ3-E)
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
1
1
2
Figure 17-14. SBF Reception
2
User’s Manual U19601EJ2V0UD
3
3
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4
5
5
6
11.5
10.5
6
7
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10
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