UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 810
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Price
Company:
Part Number:
UPD70F3785GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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808
(4) UARTCn option control register 0 (UCnOPT0)
The UCnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTCn register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
UCnOPT0
After reset: 14H
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Caution Do not set the UCnSRT and UCnSTT bits (to 1) during SBF reception
Remark
• SBF (Sync Brake Field) reception is judged during LIN communication.
• The UCnSRF bit is held at 1 when an SBF reception error occurs, and then SBF
• The UCnSRF bit is a read-only bit.
• This is the SBF reception trigger bit during LIN communication, and when read,
• Set the UCnSRT bit after setting the UCnPWR bit = UCnRXE bit = 1.
• This is the SBF transmission trigger bit during LIN communication, and when read,
• Set the UCnSTT bit after setting the UCnPWR bit = UCnTXE bit = 1.
UCnSRF
UCnSRT
UCnSRF
UCnSTT
reception.
reception is started again.
“0” is always read. For SBF reception, set the UCnSRT bit (to 1) to enable SBF
“0” is always read.
<7>
0
1
0
1
0
1
When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnRXE bit = 0 are set, or
upon normal end of SBF reception.
During SBF reception
SBF reception trigger
SBF transmission trigger
UCnSRT UCnSTT UCnSLS2 UCnSLS1 UCnSLS0 UCnTDL UCnRDL
(UCnSRF bit = 1).
n = 0 to 5 (V850ES/JH3-E)
n = 0 to 7 (V850ES/JJ3-E)
R/W
6
Address: UC0OPT0 FFFFFA03H, UC1OPT0 FFFFFA13H,
User’s Manual U19601EJ2V0UD
5
UC2OPT0 FFFFFA23H, UC3OPT0 FFFFFA33H,
UC4OPT0 FFFFFA43H, UC5OPT0 FFFFFA53H,
UC6OPT0 FFFFFA63H, UC7OPT0 FFFFFA73H
SBF transmission trigger
4
SBF reception trigger
SBF reception flag
−
−
3
2
1
0
(1/2)
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