UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 415
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
UPD70F3785GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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PWM waveform from the TOABnk pin.
newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer
register and the 16-bit counter is cleared to 0000H.
time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H.
The compare match interrupt request signal (INTTABnCCk) is generated when the count value of the 16-bit counter
matches the value of the CCRk buffer register.
TABnCTL0
TABnCTL1
When the TABnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The PWM waveform can be changed by rewriting the TABnCCRm register while the counter is operating. The
The compare match interrupt request signal (INTTABnCC0) is generated when the 16-bit counter counts up next
Remark
Active level width = (Set value of TABnCCRk register) × Count clock cycle
Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TABnCCRk register)/(Set value of TABnCCR0 register + 1)
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark
k = 1 to 3,
m = 0 to 3,
n = 0, 1
TABnSYE
TABnCE
0/1
0
n = 0, 1
TABnEST
Figure 8-26. Setting of Registers in PWM Output Mode (1/3)
0
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
TABnEEE
0/1
0
User’s Manual U19601EJ2V0UD
0
0
0
0
TABnCKS2 TABnCKS1 TABnCKS0
TABnMD2 TABnMD1 TABnMD0
0/1
1
0/1
0
0/1
0
0: Operate on count clock
1: Count by external event
1, 0, 0:
PWM output mode
Select count clock
0: Stop counting
1: Enable counting
selected by TABnCKS0 to
TABnCKS2 bits
count input signal
Note
413
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