UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 1366

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.2 Configuration
23.2.1 System configuration
The Ethernet controller supports the MII (Media Independent Interface) of IEEE802.3 and can create a 10 Mbps or
100 Mbps Ethernet environment when it is connected to a PHY device conforming to MII. In addition, data can be
communicated in full-duplex or half-duplex mode, which can be selected.
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The Ethernet controller transmits or receives data by using a dedicated direct memory access controller (DMAC).
(1) MAC
(2) FIFO controller
(3) DMAC in Ethernet controller
Caution The DMAC in the Ethernet controller processes all the data the Ethernet controller transmits and
This unit executes MAC functions and supports MII-based interfacing with an external PHY device.
• Receive checksum unit
This unit controls the transmit/receive FIFO buffers.
A 2 KB FIFO is available for both transmission and reception.
This DMA controller controls data transmission and reception to and from the internal bus.
This unit calculates the receive checksum.
receives. Data cannot be transmitted or received in packet units by reading or writing a register.
Ethernet
controller
DMAC in
Figure 23-1. Configuration of Ethernet Controller
CHAPTER 23 ETHERNET CONTROLLER
FIFO (2 KB)
FIFO (2 KB)
controller
Transmit
Receive
FIFO
User’s Manual U19601EJ2V0UD
checksum
Receive
MAC
unit
MII I/O
buffer
PHY
TPO+
TPO−
TPI+
TPI−