UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 765

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Pointer mode
(ii) During reception (reading from receive FIFO)
(i) During transmission (writing to transmit FIFO)
Remark
• If data for the first reception end interrupt request signal (INTUBnTIR) is not read from receive
• In the pending mode, receive data of the number set as the trigger by the UBnFIC2.UBnRT3 to
• Fix the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits to 0000 (set number of receive data: 1 byte) to
• Each time the data of 1 byte is transferred to the transmit shift register from transmit FIFO, a
• In the pointer mode, be sure to fix the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits to 0000 (set
• Writing transmit data to transmit FIFO by DMA is prohibited. The operation is not guaranteed if
• After the transmission enable interrupt request signal (INTUBnTIT) has been acknowledged, data
FIFO, the second INTUBnTIR signal does not occur (is held pending) even if the generation
condition of the second INTUBnTIR is satisfied (if receive data of the number set as the trigger by
the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits can be read from receive FIFO). When data for
the first INTUBnTIR signal is later read from the receive FIFO, the pending INTUBnTIR signal is
generated
Note The number of pending interrupts is as follows.
UBnFIC2.UBnRT0 bits is always read from receive FIFO when the reception end interrupt request
signal (INTUBnTIR) occurs. Reading data from receive FIFO is prohibited if the data is more or
less than the specified number. If data more or less than the specified number is read, the
operation is not guaranteed.
read receive data from receive FIFO by DMA. If any other setting is made, the operation is not
guaranteed.
transmission enable interrupt request signal (INTUBnTIT) occurs.
number of transmit data: 1 byte) as the number of transmit data set as the trigger for transmit FIFO
when the transmission enable interrupt request signal (INTUBnTIT) occurs. If any other setting is
made, the operation is not guaranteed.
DMA control is used.
of the number of empty bytes of transmit FIFO can be written to transmit FIFO by referencing the
UBnFIS1 register.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
n = 0, 1
When trigger is set to 1 byte (UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits = 0000): 15 times max.
When trigger is set to 2 bytes (UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits = 0001): 7 times max.
When trigger is set to 6 bytes (UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits = 0101): 1 time max.
When trigger is set to 7 bytes (UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits = 0110): 1 time max.
When trigger is set to 8 bytes (UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits = 0111): 1 time max.
Note
.
User’s Manual U19601EJ2V0UD
:
763