UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 309
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3785GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and a capture interrupt request
signal (INTTAAnCCm) is generated.
generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction by software.
When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
Remark
INTTAAnCC1 signal
INTTAAnCC0 signal
TAAnCCR1 register
TAAnCCR0 register
INTTAAnOV signal
TIAAn0 pin input
TIAAn1 pin input
16-bit counter
TAAnOVF bit
Figure 7-35. Basic Timing in Free-Running Timer Mode (Capture Function)
TAAnCE bit
n = 0 to 5
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
User’s Manual U19601EJ2V0UD
D
00
D
CLR instruction
Cleared to 0 by
10
D
00
D
D
01
10
D
11
CLR instruction
Cleared to 0 by
D
D
01
02
D
11
D
12
CLR instruction
Cleared to 0 by
D
02
D
D
03
12
D
13
D
03
D
13
307
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