UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 296

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

294
(2) Operation timing in one-shot pulse output mode
External trigger input
INTTAAnCC0 signal
INTTAAnCC1 signal
(only when software
TAAnCCR0 register
TAAnCCR1 register
TOAAn0 pin output
TOAAn1 pin output
(TIAAn0 pin input)
(a) Note on rewriting TAAnCCRm register
trigger is used)
16-bit counter
To change the set value of the TAAnCCRm register to a smaller value, stop counting once, and then
change the set value.
If the value of the TAAnCCRm register is rewritten to a smaller value during counting, the 16-bit counter
may overflow.
When the TAAnCCR0 register is rewritten from D
where D
counter is greater than D
value is greater than D
rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again
from 0000H. When the count value matches D
asserts the TOAAn1 pin. When the count value matches D
signal, deasserts the TOAAn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark
TAAnCE bit
FFFFH
0000H
00
n = 0 to 5
m = 0, 1
> D
01
and D
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
01
10
11
and less than D
> D
Delay
(D
and less than D
D
10
11
10
)
Active level width
(D
, if the TAAnCCR1 register is rewritten when the count value of the 16-bit
00
User’s Manual U19601EJ2V0UD
D
− D
00
10
+ 1)
D
00
10
, each set value is reflected as soon as the register has been
10
D
00
Delay
(D
and if the TAAnCCR0 register is rewritten when the count
D
10
11
10
)
Active level width
(D
00
, the counter generates the INTTAAnCC1 signal and
00
to D
D
− D
00
10
01
+ 1)
and the TAAnCCR1 register from D
01
, the counter generates the INTTAAnCC0
D
Delay
(10000H + D
10
D
00
11
)
Active level width
(D
D
D
D
11
11
01
01
D
− D
01
11
+ 1)
10
to D
11