DF2166VTE33 Renesas Electronics America, DF2166VTE33 Datasheet - Page 613
![MCU FLASH 3V 512K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VTE33
Manufacturer Part Number
DF2166VTE33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
- Current page: 613 of 876
- Download datasheet (5Mb)
Slave confirms the rising edge of the BUSY bit in SMICFLG.
The BUSYI bit in SMICIR0 is set.
Slave clears the RX_DATA_RDY bit in SMICFLG.
Slave writes transfer data to SMICDTR according to
Read control code.
Slave writes the status code to SMICCSR to notify the
processing completion status.
Slave clears the BUSY bit in SMICFLG to indicate transfer
completion.
Slave confirms that valid data is read from SMICDTR
by host.
The HDTRI bit in SMICIR0 is set.
Slave confirms that status code is read from SMICCSR
by host.
The STARI bit in SMICIR0 is set.
Slave confirms that control code is written to SMICCSR
by host.
The CTLWI bit in SMICIR0 is set.
Slave reads the control code in SMICCSR.
Slave waits for the BUSY bit in SMICFLG is set.
Bit that indicates slave is ready for read transfer.
Issues when slave is ready for the next read transfer.
Slave
Figure 16.5 SMIC Read Transfer Flow
A
A
Abnormal
RX_DATA_RDY = 0
RX_DATA_RDY = 1
Read transfer data
Wait for BUSY = 0
Write control code
Read control code
Write transfer data
Write status code
Read status code
Generate slave
Generate slave
Generate slave
Generate slave
Generate host
BUSY = 1
BUSY = 0
Waits for
interrupt
interrupt
interrupt
interrupt
interrupt
Normal
Host reads transfer data in SMICDTR.
Host confirms the BUSY bit in SMICFLG.
The bit indicates slave (this LSI) is ready for receiving a new control code.
When BUSY = 1, access from host is disabled.
Host confirms the RX_DATA_RDY bit in SMICFLG.
Host writes the Read control code to SMICCSR.
Host sets the BUSY bit in SMICFLG.
Host confirms the falling edge of the BUSY bit in SMICFLG.
An interrupt is generated.
Host confirms the status code in SMICCSR.
In the case of normal completion, the status code is reflected to the next step.
In the case of abnormal completion, the status code is READY and an error
is kept.
Rev. 3.00, 03/04, page 571 of 830
Host
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