DF2166VTE33 Renesas Electronics America, DF2166VTE33 Datasheet - Page 580
![MCU FLASH 3V 512K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VTE33
Manufacturer Part Number
DF2166VTE33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
- Current page: 580 of 876
- Download datasheet (5Mb)
Rev. 3.00, 03/04, page 538 of 830
Bit
2
1
Bit Name Initial Value Slave Host Description
SMIE2
IRQ12E1 0
0
R/W
R/W
R/W
Host SMI Interrupt Enable 2
Enables or disables a host SMI interrupt request
when OBF2 is set by an ODR2 write.
0: Host SMI interrupt request by OBF2 and SMIE2 is
[Clearing conditions]
•
•
•
1: [When IEDIR = 0]
[Setting condition]
•
Host IRQ12 Interrupt Enable 1
Enables or disables a HIRQ12 interrupt request
when OBF1 is set by an ODR1 write.
0: HIRQ12 interrupt request by OBF1 and IRQ12E1
[Clearing conditions]
•
•
•
1: HIRQ12 interrupt request by setting OBF1 to 1 is
[Setting condition]
•
disabled
Host SMI interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
Host SMI interrupt is requested
is disabled
enabled
Writing 0 to SMIE2
LPC hardware reset, LPC software reset
Clearing OBF2 to 0 (when IEDIR = 0)
Writing 1 after reading SMIE2 = 0
Writing 0 to IRQ12E1
LPC hardware reset, LPC software reset
Clearing OBF1 to 0
Writing 1 after reading IRQ12E1 = 0
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