DF2166VTE33 Renesas Electronics America, DF2166VTE33 Datasheet - Page 24
![MCU FLASH 3V 512K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VTE33
Manufacturer Part Number
DF2166VTE33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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20.6 Switching between User MAT and User Boot MAT........................................................ 668
20.7 Programmer Mode ............................................................................................................ 669
20.8 Serial Communication Interface Specification for Boot Mode......................................... 670
20.9 Usage Notes ...................................................................................................................... 695
Section 21 Boundary Scan (JTAG) ................................................................... 697
21.1 Features............................................................................................................................. 697
21.2 Input/Output Pins.............................................................................................................. 699
21.3 Register Descriptions........................................................................................................ 700
21.4 Operation .......................................................................................................................... 714
21.5 Boundary Scan.................................................................................................................. 715
21.6 Usage Notes ...................................................................................................................... 718
Section 22 Clock Pulse Generator..................................................................... 721
22.1 Oscillator........................................................................................................................... 722
22.2 PLL Multiplier Circuit ...................................................................................................... 724
22.3 Medium-Speed Clock Divider .......................................................................................... 724
22.4 Bus Master Clock Select Circuit....................................................................................... 724
22.5 Subclock Input Circuit ...................................................................................................... 724
22.6 Subclock Waveform Forming Circuit............................................................................... 724
22.7 Clock Select Circuit .......................................................................................................... 725
22.8 Usage Notes ...................................................................................................................... 725
Section 23 Power-Down Modes........................................................................ 727
23.1 Register Descriptions........................................................................................................ 728
Rev. 3.00, 03/04, page xxii of xl
20.5.1 Hardware Protection ............................................................................................ 665
20.5.2 Software Protection ............................................................................................. 666
20.5.3 Error Protection ................................................................................................... 666
21.3.1 Instruction Register (SDIR) ................................................................................. 701
21.3.2 Bypass Register (SDBPR) ................................................................................... 703
21.3.3 Boundary Scan Register (SDBSR) ...................................................................... 703
21.3.4 ID Code Register (SDIDR).................................................................................. 713
21.4.1 TAP Controller State Transitions......................................................................... 714
21.4.2 JTAG Reset.......................................................................................................... 715
21.5.1 Supported Instructions ......................................................................................... 715
22.1.1 Connecting Crystal Resonator ............................................................................. 722
22.1.2 External Clock Input Method .............................................................................. 723
22.8.1 Note on Resonator ............................................................................................... 725
22.8.2 Notes on Board Design ........................................................................................ 725
22.8.3 Note on Operation Check .................................................................................... 726
23.1.1 Standby Control Register (SBYCR) .................................................................... 728
23.1.2 Low-Power Control Register (LPWRCR) ........................................................... 730
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