DF2166VTE33 Renesas Electronics America, DF2166VTE33 Datasheet - Page 308
![MCU FLASH 3V 512K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VTE33
Manufacturer Part Number
DF2166VTE33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
- Current page: 308 of 876
- Download datasheet (5Mb)
10.3.3
DACR enables the PWM outputs, and selects the output phase and operating speed.
Rev. 3.00, 03/04, page 266 of 830
Bit
7
6
5, 4
3
2
1
0
Bit Name
PWME
OEB
OEA
OS
CKS
PWMX (D/A) Control Register (DACR)
Initial Value
0
0
All 1
0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
The initial value should not be changed.
PWMX Enable
Starts or stops the PWM D/A counter (DACNT).
0: DACNT operates as a 14-bit up-counter
1: DACNT halts at H'0003
Reserved
These bits are always read as 1 and cannot be
modified.
Output Enable B
Enables or disables output on PWMX (D/A) channel B.
0: PWMX (D/A) channel B output (at the PWX1, PWX3
1: PWMX (D/A) channel B output (at the PWX1, PWX3
Output Enable A
Enables or disables output on PWMX (D/A) channel A.
0: PWMX (D/A) channel A output (at the PWX0, PWX2
1: PWMX (D/A) channel A output (at the PWX0, PWX2
Output Select
Selects the phase of the PWMX (D/A) output.
0: Direct PWMX (D/A) output
1: Inverted PWMX (D/A) output
Clock Select
Selects the PWMX (D/A) resolution. Eight kinds of
resolution can be selected.
0: Operates at resolution (T) = system clock cycle time
1: Operates at resolution (T) = system clock cycle time
pins) is disabled
pins) is enabled
pin) is disabled
pins) is enabled
(t
(t
16384.
cyc
cyc
)
) × 2, × 64, × 128, × 256, × 1024, × 4096, and ×
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