DF2166VTE33 Renesas Electronics America, DF2166VTE33 Datasheet - Page 465
![MCU FLASH 3V 512K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VTE33
Manufacturer Part Number
DF2166VTE33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
- Current page: 465 of 876
- Download datasheet (5Mb)
14.10.6 Restrictions on Using DTC
When the external clock source is used as a synchronization clock, update TDR by the DTC and
wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit
clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure
14.38).
When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC
activation source.
14.10.7 SCI Operations during Mode Transitions
Transmission: Before making the transition to module stop, software standby, or sub-sleep mode,
stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of
the output pins during each mode depend on the port settings, and the pins output a high-level
signal after mode cancellation. If the transition is made during data transmission, the data being
transmitted will be undefined.
To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR,
write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different
transmission mode, initialize the SCI first.
Figure 14.39 shows a sample flowchart for mode transition during transmission. Figures 14.40 and
14.41 show the pin states during transmission.
Before making the transition from the transmission mode using DTC transfer to module stop,
software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting
TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission
using the DTC.
Figure 14.38 Sample Transmission using DTC in Clock Synchronous Mode
SCK
TDRE
Serial data
Note: When external clock is supplied, t must be more than four clock cycles.
t
LSB
D0
D1
D2
D3
D4
Rev. 3.00, 03/04, page 423 of 830
D5
D6
D7
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