HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 93

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

3.5.4
An initial page write exception results in a write access when the virtual address and the address
array of the selected TLB entry are compared and a valid entry with the appropriate access rights
is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial
page write exception handling includes both hardware and software operations.
Hardware Operations: In an initial page write exception, the SH7708 Series hardware executes a
set of prescribed operations, as follows:
1. The VPN field of the virtual address causing the exception is written to the PTEH register.
2. The virtual address causing the exception is written to the TEA register.
3. Exception code H'080 is written to the EXPEVT register.
4. The PC value indicating the address of the instruction in which the exception occurred is
5. The contents of SR at the time of the exception are written to SSR.
6. The MD bit in SR is set to 1 to place the SH7708 Series in privileged mode.
7. The BL bit in SR is set to 1 to mask any further exception requests.
8. The register bank (RB) bit in SR is set to 1.
9. The way that caused the exception is set in the RC field in MMUCR.
10. Execution branches to the address obtained by adding the value of the VBR contents and
Software (Initial Page Write Handler) Operations: The software must execute the following
operations:
1. Retrieve the required page table entry from external memory.
2. Set the D bit of the page table entry in external memory to 1.
3. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table entry in
4. If using software for way selection for entry replacement, write the desired value to the RC
5. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
6. Issue the RTE instruction to terminate the handler and return to the instruction stream. The
Figure 3.11 shows the flowchart for MMU exceptions.
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the related delayed branch instruction is written to the SPC.
H'00000100 to invoke the user-written initial page write exception handler.
external memory to the PTEL register.
field in MMUCR.
RTE instruction should be issued after two LDTLB instructions.
Initial Page Write Exception
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