HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 158
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number:
HD6417708RF100AV
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7.3.5
Register settings, set conditions, and states in which the set conditions are matched, are as follows:
1. Instruction fetch cycle break condition setting (independent channel A and B conditions)
2. Instruction fetch cycle break condition setting (independent channel A and B conditions)
138
A user break is generated after execution of the instruction at address H'00000404 with
ASID = H'80, or before execution of instructions at addresses H'00008000 to H'000083FE with
ASID = H'70.
A user break is generated before execution of the instruction at address H'0003722E with
BRCR = H'0400: Independent channel A and B conditions, post-execution for channel A,
Channel A:
Channel B:
BRCR = H'0080: Channel A
Channel A:
Channel B:
Examples of Use
pre-execution for channel B
BASRA = H'80:
BARA = H'00000404:
BAMRA = H'00:
BBRA = H'0014:
BASRB = H'70:
BARB = H'00008010:
BAMRB = H'02:
BBRB = H'0014:
BDRB = H'00000000:
BDMRB = H'00000000: Data mask H'00000000
A, pre-execution for channel B
BASRA = H'80:
BARA = H'00037226:
BAMRA = H'00:
BBRA = H'0016:
BASRB = H'70:
BARB = H'0003722E:
BAMRB = H'00:
BBRB = H'0016:
BDRB = H'00000000:
BDMRB = H'00000000: Data mask H'00000000
channel B sequential conditions, pre-execution for channel
ASID H'80
Address H'00000404
Address mask H'00
Bus cycle, instruction fetch (post-execution),
read (operand size not included in conditions)
ASID H'70
Address H'00008010
Address mask H'02
Bus cycle, instruction fetch (pre-execution),
read (operand size not included in conditions)
Data H'00000000
ASID H'80
Address H'00037226
Address mask H'00
Bus cycle, instruction fetch (pre-execution),
read, word
ASID H'70
Address H'0003722E
Address mask H'00
Bus cycle, instruction fetch (pre-execution),
read, word
Data H'00000000
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