HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 320
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
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10.4.5
When area 2 or area 3 is connected to DRAM in the SH7708 or SH7708S, if a DRAM access
request occurs immediately after a CAS-before-RAS refresh, the RAS precharge cycle value (tPC)
always assumes its initial value regardless of the value set in MCR. Thus, the interval from RAS
negation to the next RAS assertion in CAS-before-RAS refreshing is a two-cycle output interval
(see figure below).
If a request does not immediately follow a CAS-before-RAS refresh, the number of RAS
precharge cycles set by the MCR value are secured.
Restriction: If a DRAM access request occurs immediately after a CAS-before-RAS refresh, the
interval from RAS negation to the next RAS assertion is two cycles.
300
CKIO
RAS
Note on DRAM Connection for Areas 2 and 3
RAS negation
in CAS-before-
RAS refreshing
Two cycles
RAS asserted by
next bus access
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