HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 229
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708RF100A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708RF100A
Manufacturer:
HITACHI/日立
Quantity:
20 000
Part Number:
HD6417708RF100AV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Bit 4: A1-2W0
0
1
Bit 4: A1-2W0
0
1
Bits 2 to 0—Area 0 Wait Control (A0W2, A0W1, A0W0): These bits specify the number of wait
states inserted in physical space area 0. They also specify the burst pitch for burst transfer.
Bit 2:
A0W2
0
1
10.2.5
The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS
and CAS timing and burst control for DRAM (area 3 only), synchronous DRAM (areas 2 and 3),
For Normal Memory
For DRAM, Synchronous DRAM
Bit 1:
A0W1
0
1
0
1
Individual Memory Control Register (MCR)
Bit 3: A1-2W0
0
1
0
1
Bit 0:
A0W0
0
1
0
1
0
1
0
1
Bit 3: A1-2W0
0
1
0
1
Inserted
Wait States
0
1
2
3
4
6
8
10 (Initial value) Enabled
DRAM: CAS Assert Period
1
1
2
3
First Cycle
WAIT Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Inserted Wait States
0
1
2
3
Description
Number of States
Per Data Transfer
2
2
3
4
4
6
8
10
Description
Description
(Excluding First Cycle)
SDRAM: CAS Latency
1
1
2
3
Burst Cycle
WAIT Pin
Ignored
Enabled
Enabled
Enabled (Initial value)
(Initial value)
WAIT Pin
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
209
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