HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 226

IC SUPERH MPU ROMLESS 144LQFP

HD6417708RF100A

Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417708RF100A

Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

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10.2.4
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in
standby mode, but retains its contents.
Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): These bits specify the number of
wait states inserted in physical space area 6. They also specify the burst pitch for burst transfer.
Bit 15:
A6W2
0
1
206
Initial value:
Initial value:
Bit name:
Bit name:
Bit 14:
A6W1
0
1
0
1
Wait State Control Register 2 (WCR2)
R/W:
R/W:
Bit:
Bit:
Bit 13:
A6W0
0
1
0
1
0
1
0
1
A6W2
A4W0
R/W
R/W
15
1
7
1
Inserted
Wait States
0
1
2
3
4
6
8
10 (Initial value) Enabled
A6W1
A3W1
R/W
R/W
14
1
6
1
First Cycle
A6W0
A3W0
R/W
R/W
13
1
5
1
WAIT Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
A1-2W1 A1-2W0
A5W2
R/W
R/W
12
1
4
1
Description
A5W1
R/W
R/W
Number of States
Per Data Transfer
2
2
3
4
4
6
8
10
11
1
3
1
(Excluding First Cycle)
A5W0
A0W2
R/W
R/W
10
1
2
1
Burst Cycle
A4W2
A0W1
R/W
R/W
9
1
1
1
WAIT Pin
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
A4W1
A0W0
R/W
R/W
8
1
0
1

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